Visible to Intel only — GUID: mwh1409959064897
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Visible to Intel only — GUID: mwh1409959064897
Ixiasoft
4.5. Using Bridges
An Avalon® bridge has an Avalon® memory mapped agent interface and an Avalon® memory mapped host interface. You can have many components connected to the bridge agent interface, or many components connected to the bridge host interface. You can also have a single component connected to a single bridge agent or host interface.
You can configure the data width of the bridge, which can affect how Platform Designer generates bus sizing logic in the interconnect. Both interfaces support Avalon® memory mapped pipelined transfers with variable latency, and can also support configurable burst lengths.
Transfers to the bridge agent interface are propagated to the host interface, which connects to components downstream from the bridge. Bridges can provide more control over interconnect pipelining than the Limit interconnect pipeline stages to option.