Visible to Intel only — GUID: mwh1409958833282
Ixiasoft
Visible to Intel only — GUID: mwh1409958833282
Ixiasoft
5.1.1.1. Fields in the Platform Designer Packet Format
Command | Description |
---|---|
Address | Specifies the byte address for the lowest byte in the current cycle. There are no restrictions on address alignment. |
Size | Encodes the run-time size of the transaction. In conjunction with address, this field describes the segment of the payload that contains valid data for a beat within the packet. |
Address Sideband | Carries “address” sideband signals. The interconnect passes this field from host to agent. This field is valid for each beat in a packet, even though it is only produced and consumed by an address cycle. Up to 8-bit sideband signals are supported for both read and write address channels. |
Cache | Carries the AXI cache signals. |
Transaction (Exclusive) | Indicates whether the transaction has exclusive access. |
Transaction (Posted) | Used to indicate non-posted writes (writes that require responses). |
Data | For command packets, carries the data to be written. For read response packets, carries the data that has been read. |
Byteenable | Specifies which symbols are valid. AXI can issue or accept any byteenable pattern. For compatibility with Avalon® , Intel recommends that you use the following legal values for 32-bit data transactions between Avalon® hosts and agents:
|
Source_ID | The ID of the host or agent that initiated the command or response. |
Destination_ID | The ID of the host or agent to which the command or response is directed. |
Response | Carries the AXI response signals. |
Thread ID | Carries the AXI transaction ID values. |
Byte count | The number of bytes remaining in the transaction, including this beat. Number of bytes requested by the packet. |
Burstwrap | The burstwrap value specifies the wrapping behavior of the current burst. The burstwrap value is of the form 2<n> -1. The following types are defined:
For Avalon® hosts, Platform Designer adaptation logic sets a hardwired value for the burstwrap field, according the declared host burst properties. For example, for a host that declares sequential bursting, the burstwrap field is set to ones. Similarly, hosts that declare burst have their burstwrap field set to the appropriate constant value. AXI masters choose their burst type at run-time, depending on the value of the AW or ARBURST signal. The interconnect calculates the burstwrap value at run-time for AXI masters. |
Protection | Access level protection. When the lowest bit is 0, the packet has normal access. When the lowest bit is 1, the packet has privileged access. For Avalon® memory mapped interfaces, this field maps directly to the privileged access signal, which allows a memory-mapped host to write to an on‑chip memory ROM instance. The other bits in this field support AXI secure accesses and uses the same encoding, as described in the AXI specification. |
QoS | QoS (Quality of Service Signaling) is a 4-bit field that is part of the AMBA* 4 AXI interface that carries QoS information for the packet from the AXI master to the AXI slave. Transactions from AMBA* 3 AXI and Avalon® hosts have the default value 4'b0000, that indicates that they are not participating in the QoS scheme. QoS values are dropped for agents that do not support QoS. |
Data sideband | Carries data sideband signals for the packet. On a write command, the data sideband directly maps to WUSER. On a read response, the data sideband directly maps to RUSER. On a write response, the data sideband directly maps to BUSER. |