Visible to Intel only — GUID: mwh1409959238884
Ixiasoft
Visible to Intel only — GUID: mwh1409959238884
Ixiasoft
8.2.8. Port Properties
Type | Name | Description |
---|---|---|
(various) | DIRECTION | The direction of the port from the IP component's perspective. Refer to Direction Properties. |
String | DRIVEN_BY | Indicates that this output port is always driven to a constant value or by an input port. If all outputs on an IP component specify a driven_by property, the HDL for the IP component is generated automatically. |
String[] | FRAGMENT_LIST | This property can be used in 2 ways: First you can take a single RTL signal and split it into multiple Platform Designer signals add_interface_port <interface> alpha <role> <direction> <width> add_interface_port <interface> bar <role> <direction> <width> set_port_property alpha fragment_list "my_rtl_signal(3:0)" set_port_property bar fragment_list "my_rtl_signal(6:4)" Second you can take multiple RTL signals and combine them into a single Platform Designer signal add_interface_port <interface> baz <role> <direction> <width> set_port_property baz fragment_list "rtl_signal_1(3:0) rtl_signal_2(3:0)" Note: The listed bits in a port fragment must match the declared width of the Platform Designer signal. |
String | ROLE | Specifies an Avalon signal type such as waitrequest, readdata, or read. For a complete list of signal types, refer to the Avalon Interface Specifications. |
String | SV_INTERFACE_PORT | This port from the module is used as I/O in the SystemVerilog interface instantiation. The top-level wrapper of the module which contains this port is from the SystemVerilog interface. Example: |
String | SV_INTERFACE_PORT_NAME | This property is used only when the Platform Designer port name defined for the module is different from the port name in the SystemVerilog interface. Example: When writing the RTL, the Platform Designer port name port_x is mapped to RTL name port_a in the SystemVerilog interface |
String | SV_INTERFACE_SIGNAL | This port from the module is assumed to be inside the SystemVerilog interface or the modport used by the module. The top-level wrapper of the module containing this port is unwrapped from SystemVerilog interface. Example: |
String | SV_INTERFACE_SIGNAL_NAME | This property is only used when the Platform Designer port name defined for the module is different from the port name in the SystemVerilog interface. Example: |
Boolean | TERMINATION | When true, instead of connecting the port to the Platform Designer system, it is left unconnected for output and bidir or set to a fixed value for input. Has no effect for IP components that implement a generation callback instead of using the default wrapper generation. |
BigInteger | TERMINATION_VALUE | The constant value to drive an input port. |
(various) | VHDL_TYPE | Indicates the type of a VHDL port. The default value, auto, selects std_logic if the width is fixed at 1, and std_logic_vector otherwise. Refer to Port VHDL Type Properties. |
String | WIDTH | The width of the port in bits. Cannot be set directly. Any changes must be set through the WIDTH_EXPR property. |
String | WIDTH_EXPR | The width expression of a port. The width_value_expr property can be set directly to a numeric value if desired. When get_port_property is used width always returns the current integer width of the port while width_expr always returns the unevaluated width expression. |
Integer | WIDTH_VALUE | The width of the port in bits. Cannot be set directly. Any changes must be set through the WIDTH_EXPR property. |