Visible to Intel only — GUID: mwh1409959263583
Ixiasoft
Visible to Intel only — GUID: mwh1409959263583
Ixiasoft
6.1. Bridges
Bridges affect the way Platform Designer transports data between components. You can insert bridges between host11 and agent interfaces to control the topology of a Platform Designer system, which affects the interconnect that Platform Designer generates. You can also use bridges to separate components into different clock domains to isolate clock domain crossing logic.
A bridge has one agent interface and one host interface. In Platform Designer, one or more host interfaces from other components connect to the bridge agent. The bridge host connects to one or more agent interfaces on other components. In the following example, three hosts have logical connections to three agents, although physically each host connects only to the bridge. Transfers initiated to the agent propagate to the host in the same order in which the transfers are initiated on the agent.
- Clock Bridge Intel FPGA IP
- Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP
- Avalon Memory Mapped Pipeline Bridge Intel FPGA IP
- Avalon Memory Mapped Unaligned Burst Expansion Bridge Intel FPGA IP
- Bridges Between Avalon and AXI Interfaces
- AXI Bridge Intel FPGA IP
- AXI Timeout Bridge Intel FPGA IP
- Address Span Extender Intel FPGA IP