Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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6.10.3. Avalon® Streaming Demultiplexer Intel® FPGA IP

The Avalon® Streaming Demultiplexer Intel® FPGA IP takes data from a channelized input data interface and provides that data to multiple output interfaces, where the output interface selected for a particular transfer is specified by the input channel signal.

Figure 237.  Avalon® Streaming Demultiplexer

The data is delivered to the output interfaces in the same order it is received at the input interface, regardless of the value of channel, packet, frame, or any other signal. Each of the output interfaces has the same width as the input interface; each output interface is idle when the demultiplexer is driving data to a different output interface. The demultiplexer uses log2 (num_output_interfaces) bits of the channel signal to select the output for the data; the remainder of the channel bits are forwarded to the appropriate output interface unchanged.