Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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6.6.1. Avalon® Streaming Delay Intel® FPGA IP Reset Signal

The Avalon® Streaming Delay Intel® FPGA IP has a reset signal that is synchronous to the clk signal. When the IP asserts the reset signal, the output signals are held at 0. After the reset signal is deasserted, the output signals are held at 0 for N clock cycles. The delayed values of the input signals are then reflected at the output signals after N clock cycles.