Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.3.2. Tri-State Conduit Pin Sharer Intel® FPGA IP

The Tri-State Conduit Pin Sharer Intel® FPGA IP multiplexes between the signals of the connected tri-state controllers. You connect all signals from the tri-state controllers to the Tri-State Conduit Pin Sharer IP, and then use the parameter editor to specify the signals that are shared.

The parameter editor includes a Shared Signal Name column. If the widths of shared signals differ, the signals are aligned on their 0th bit and the higher-order pins are driven to 0 whenever the smaller signal has control of the bus. Unshared signals always propagate through the pin sharer. The tri-state conduit pin sharer uses the round-robin arbiter to select between tri-state conduit controllers.

Figure 227. Tri-State Conduit Pin Sharer Parameter Editor
Note: All tri-state conduit components connected to a pin sharer must be in the same clock domain.