Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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6.6.3. Avalon® Streaming Delay Intel® FPGA IP Parameters

Table 181.   Avalon® Streaming Delay Intel® FPGA IP Parameters

Parameter

Legal Values

Default Value

Description

Number Of Delay Clocks

0 to 16

1

Specifies the delay the IP introduces, in clock cycles. Platform Designer supports 0 for some systems where no delay is required.

Data Width

1–512

8

The width of the data on the Avalon® streaming data interfaces.

Bits Per Symbol

1–512

8

The number of bits per symbol for the input and output interfaces. For example, byte-oriented interfaces have 8-bit symbols.

Use Packets

0 or 1

0

Indicates whether data packet transfers are supported. Packet support includes the startofpacket, endofpacket, and empty signals.

Use Channel

0 or 1

0

The option to enable or disable the channel signal.

Channel Width

0-8

1

The width of the channel signal on the data interfaces. This parameter is disabled when Use Channel is set to 0.

Max Channels

0-255

1

The maximum number of channels that a data interface can support. This parameter is disabled when Use Channel is set to 0.

Use Error

0 or 1

0

The option to enable or disable the error signal.

Error Width

0–31

1

The width of the error signal on the output interfaces. A value of 0 indicates that the error signal is not in use. This parameter is disabled when Use Error is set to 0.