Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.5.4.4. Address Coherency

To simplify the system design, all hosts should access agents at the same location. In many systems, a processor passes buffer locations to other hosting components, such as a DMA controller. If the processor and DMA controller do not access the agent at the same location, Platform Designer must compensate for the differences.

Figure 130. Slaves at Different Addresses and Complicating the System

A Nios® II processor and DMA controller access an agent interface located at address 0x20. The processor connects directly to the agent interface. The DMA controller connects to a pipeline bridge located at address 0x1000, which then connects to the agent interface. Because the DMA controller accesses the pipeline bridge first, it must drive 0x1020 to access the first location of the agent interface. Because the processor accesses the agent from a different location, you must maintain two base addresses for the agent device.

To avoid the requirement for two addresses, you can add an additional bridge to the system, set its base address to 0x1000, and then disable all the pipelining options in the second bridge so that the bridge has minimal impact on system timing and resource utilization. Because this second bridge has the same base address as the original bridge, the processor and DMA controller access the agent interface with the same address range.

Figure 131. Address Translation Corrected With Bridge