Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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4.6.2.2.2. Pipelined Avalon® Memory Mapped Interfaces

Pipelined read transfers allow a pipelined host interface to start multiple read transfers in succession without waiting for prior transfers to complete. Pipelined transfers allow host-agent pairs to achieve higher throughput, even though the agent port may require one or more cycles of latency to return data for each transfer.

In many systems, read throughput becomes inadequate if simple reads are used and pipelined transfers can increase throughput. If you define a component with a fixed read latency, Platform Designer automatically provides the pipelining logic necessary to support pipelined reads. You can use fixed latency pipelining as the default design starting point for agent interfaces. If your agent interface has a variable latency response time, use the readdatavalid signal to indicate when valid data is available. The interconnect implements read response FIFO buffering to handle the maximum number of pending read requests.

To use components that support pipelined read transfers, and to use a pipelined system interconnect efficiently, your system must contain pipelined hosts. You can use pipelined hosts as the default starting point for new host components. Use the readdatavalid signal for these host interfaces.

Because host and agents sometimes have mismatched pipeline latency, the interconnect contains logic to reconcile the differences.

Table 39.  Pipeline Latency in a Host-Agent Pair
Host Agent Pipeline Management Logic Structure
No pipeline No pipeline Platform Designer interconnect does not instantiate logic to handle pipeline latency.
No pipeline Pipelined with fixed or variable latency Platform Designer interconnect forces the host to wait through any agent-side latency cycles. This host-agent pair gains no benefits from pipelining, because the host waits for each transfer to complete before beginning a new transfer. However, while the host is waiting, the agent can accept transfers from a different host.
Pipelined No pipeline Platform Designer interconnect carries out the transfer as if neither host nor agent were pipelined, causing the host to wait until the agent returns data. An example of a non-pipeline agent is an asynchronous off-chip interface.
Pipelined Pipelined with fixed latency Platform Designer interconnect allows the host to capture data at the exact clock cycle when data from the agent is valid, to enable maximum throughput. An example of a fixed latency agent is an on-chip memory.
Pipelined Pipelined with variable latency The agent asserts a signal when its readdata is valid, and the host captures the data. The host-agent pair can achieve maximum throughput if the agent has variable latency. Examples of variable latency agents include SDRAM and FIFO memories.