Visible to Intel only — GUID: mwh1409959063244
Ixiasoft
Visible to Intel only — GUID: mwh1409959063244
Ixiasoft
4.3.3. Implementing Concurrency with DMA Engines
In some systems, you can use DMA engines to increase throughput. You can use a DMA engine to transfer blocks of data between interfaces, which then frees the CPU from doing this task. A DMA engine transfers data between a programmed start and end address without intervention, and the data throughput is dictated by the components connected to the DMA. Factors that affect data throughput include data width and clock frequency.
In this example, the system can sustain more concurrent read and write operations by including more DMA engines. Accesses to the read and write buffers in the top system are split between two DMA engines, as shown in the Dual DMA Channels at the bottom of the figure.
The DMA engine operates with Avalon® memory mapped write and read hosts. An AXI DMA typically has only one master, because in AXI, the write and read channels on the master are independent and can process transactions simultaneously.