Visible to Intel only — GUID: mwh1409959426221
Ixiasoft
Visible to Intel only — GUID: mwh1409959426221
Ixiasoft
6.7. Avalon® Streaming Round Robin Scheduler Intel® FPGA IP
The Avalon® Streaming Round Robin Scheduler Intel® FPGA IP controls the read operations from a multi-channel Avalon® streaming component that buffers data by channels. The IP reads the almost-full threshold values from the multiple channels in the multi-channel component, and then issues the read request to the Avalon® streaming source according to a round-robin scheduling algorithm.
In a multi-channel component, the IP can store data either in the sequence that it comes in (FIFO), or in segments according to the channel. When data is stored in segments according to channels, a scheduler is needed to schedule the read operations.