Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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5.6.4.3.6. Reset Sequencer Software Direct Controlled Resets

You can write a bit to 1 to assert the reset_outN signal, and to 0 to deassert the reset_outN signal.
Table 91.  Values for the Software Direct Controlled Resets at Offset 0x14
Bit Attribute Default Description
31:26 Reserved.
25:16 WO 0 Reset Overwrite Trigger Enable—This is a per-bit control trigger bit for the overwrite value to take effect.
15:10 Reserved.
9:0 WO 0 reset_outN Reset Overwrite Value—This is a per-bit control of the reset_out bit. The Reset Sequencer can use this to forcefully drive the reset to a specific value. A value of 1 sets the reset_out. A value of 0 clears the reset_out. A write to this register only takes effect if the corresponding trigger bit in this register is set.