Visible to Intel only — GUID: mwh1409959429384
Ixiasoft
Visible to Intel only — GUID: mwh1409959429384
Ixiasoft
6.7.3. Avalon® Streaming Round Robin Scheduler IP Operation
The scheduler only requests 1 bit of data from a channel at each transaction. To request 1 bit of data from channel n, the scheduler writes the value 1 to address (4 ×n). For example, if the scheduler is requesting data from channel 3, the scheduler writes 1 to address 0xC. At every clock cycle, the scheduler requests data from the next channel. Therefore, if the scheduler starts requesting from channel 1, at the next clock cycle, it requests from channel 2. The scheduler does not request data from a particular channel if the almost-full status for the channel is asserted. In this case, the scheduler uses one clock cycle without a request transaction.
The Avalon® Streaming Round Robin Scheduler cannot determine if the requested component is able to service the request transaction. The component asserts waitrequest when it cannot accept new requests.
Signal |
Direction |
Description |
---|---|---|
Clock and Reset |
||
clk | In |
Clock reference. |
reset_n | In |
Asynchronous active low reset. |
Avalon® Memory Mapped Request Interface |
||
request_address (log2 Max_Channels–1:0) | Out |
The write address that indicates which channel has the request. |
request_write | Out |
Write enable signal. |
request_writedata | Out |
The amount of data requested from the particular channel. This value is always fixed at 1. |
request_waitrequest | In |
Wait request signal that pauses the scheduler when the agent cannot accept a new request. |
Avalon® Streaming Almost-Full Status Interface |
||
almost_full_valid | In |
Indicates that almost_full_channel and almost_full_data are valid. |
almost_full_channel (Channel_Width–1:0) | In |
Indicates the channel for the current status indication. |
almost_full_data (log2 Max_Channels–1:0) | In |
A 1-bit signal that is asserted high to indicate that the channel indicated by almost_full_channel is almost full. |