Visible to Intel only — GUID: mwh1409959117665
Ixiasoft
Visible to Intel only — GUID: mwh1409959117665
Ixiasoft
4.6.2.3. Avalon® Memory Mapped Burst Host Example
The host performs word accesses and writes to sequential memory locations. When go is asserted, the start_address and transfer_length are registered. On the next clock cycle, the control logic asserts burst_begin, which synchronizes the internal control signals in addition to the host_address and host_burstcount presented to the interconnect. The timing of these two signals is important because during bursting write transfers byteenable and burstcount must be held constant for the entire burst.
To avoid inefficient writes, the host posts a burst when enough data is buffered in the FIFO. To maximize the burst efficiency, the host should stall only when an agent asserts waitrequest. In this example, the FIFO’s used signal tracks the number of words of data that are stored in the FIFO and determines when enough data has been buffered.
The address register increments after every word transfer, and the length register decrements after every word transfer. The address remains constant throughout the burst. Because a transfer is not guaranteed to complete on burst boundaries, additional logic is necessary to recognize the completion of short bursts and complete the transfer.