Visible to Intel only — GUID: mwh1409959284046
Ixiasoft
Visible to Intel only — GUID: mwh1409959284046
Ixiasoft
6.1.4.2. Avalon® Memory Mapped Unaligned Burst Expansion Bridge Parameters
Parameter | Description |
---|---|
Data width | Data width of the host connected to the bridge. |
Address width (in WORDS) | The address width of the host connected to the bridge. |
Burstcount width | The burstcount signal width of the host connected to the bridge. |
Maximum pending read transactions | The Maximum pending read transactions parameter is the maximum number of pending reads that the Avalon® Memory Mapped bridge can queue up. To determine the best value for this parameter, review this same option for the bridge's connected agents and identify the highest value of the parameter, and then add the internal buffering requirements of the Avalon® Memory Mapped bridge. In general, the value is between 4 and 32. The limit for maximum queued transactions is 64. |
Width of agent to optimize for | The data width of the connected agent. Supported values are: 16, 32, 64, 128, 256, 512, 1024, 2048, and 4096 bits.
Note: If you connect multiple agents, all agents must have the same data width.
|
Pipeline command signals | When turned on, the command path is pipelined, minimizing the bridge's critical path at the expense of increased logic usage and latency. |