Visible to Intel only — GUID: crr1546890559023
Ixiasoft
Visible to Intel only — GUID: crr1546890559023
Ixiasoft
1.7.1. Interconnect Parameters
Option | Description |
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Enable all pipeline stages |
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Limit interconnect pipeline stages to | Specifies the maximum number of pipeline stages that Platform Designer can insert in each command and response path to increase the fMAX at the expense of additional latency. You can specify between 0 and 4 as the maximum number of pipeline stages to insert. The default value is 1. A value of 0 indicates no pipelines and a combinational datapath. When you specify 1 or greater, Platform Designer inserts up to the number you specify, depending on availability of pipeline locations.
Note: If certain adapters or IP components are not present in the interconnect, or if there are not enough pipelineable locations in the interconnect, Platform Designer does not add all of the pipeline stages specified. Click Show System with Interconnect to view the number of stages added for a particular domain.
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Clock crossing adapter type | Specifies the default implementation for automatically inserted clock crossing adapters:
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Automate default slave insertion | Directs Platform Designer to automatically insert a default slave for undefined memory region accesses during system generation. |
Enable instrumentation | When you set this option to TRUE, Platform Designer enables debug instrumentation in the Platform Designer interconnect, which then monitors interconnect performance in the system console. |
Interconnect reset source | Select Default or a specific reset signal in your design. |
Burst adapter implementation | Allows you to choose the converter type that Platform Designer applies to each burst.
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Width adapter implementation |
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Enable ECC protection | Specifies the default implementation for ECC protection for memory elements.
For more information about Error Correction Coding (ECC), refer to Error Correction Coding (ECC) in Platform Designer Interconnect. |
Use synchronous reset | When set to TRUE, all registers in the interconnect use synchronous reset. Assert the reset for at least 16 cycles and start transactions 16 cycles after deassertion of the reset. This period allows all the IP components to reset and come out of the reset state. To avoid deadlocks in the interconnect, reset masters and agents simultaneously. If masters and agents have different resets, agents must reset only after responding to all necessary transactions. The Use synchronous reset option is enabled by default for Intel® Hyperflex™ architecture devices, but is disabled by default for all other devices. Enabling synchronous reset for the interconnect does not enable synchronous reset for IP components in the system. You must separately enable the synchronous reset parameter for any component. |
Optimize size for Avalon Response Data Fifo | When set to TRUE, Platform Designer does not to increase the size of the Avalon® interface agent read FIFO to the next power of 2. Enable this setting to decrease the size of the FIFO if the FIFO becomes very large. |