Visible to Intel only — GUID: mwh1409958947830
Ixiasoft
Visible to Intel only — GUID: mwh1409958947830
Ixiasoft
5.6. Reset Interfaces
You can define separate reset sources for each clock domain, a single reset source for all clocks, or any combination in between. You can choose to create a single global reset domain by clicking System > Create Global Reset Network. If your design requires more than one reset domain, you can implement your own reset logic and connectivity. The IP Catalog includes a reset controller, reset sequencer, and a reset bridge to implement the reset functionality. You can also design your own reset logic.
Platform Designer interconnect now supports synchronous reset of registers in the interconnect. Use of synchronous reset can result in higher performance for Intel® Stratix® 10 designs because although Intel® Stratix® 10 Hyper-Registers lack a reset signal, they can make use of the synchronous reset from an adjacent LAB. If a register in your Intel® Stratix® 10 design uses asynchronous reset, the Compiler cannot implement the register as a Hyper-Register, potentially reducing performance.
When Use synchronous reset is set to True in the Domains tab, all registers in the interconnect use synchronous reset. The Use synchronous reset option is enabled by default for Intel® Stratix® 10 designs, but is disabled by default for all other designs.