Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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4.3.1. Implementing Concurrency With Multiple Hosts

Implementing concurrency requires multiple hosts in a Platform Designer system. Systems that include a processor contain at least two host interfaces because the processors include separate instruction and data hosts. You can categorize host components as follows:

  • General purpose processors, such as Nios® II processors
  • DMA (direct memory access) engines
  • Communication interfaces, such as PCI Express
Because Platform Designer generates an interconnect with agent-side arbitration, every host interface in a system can issue transfers concurrently, if they are not posting transfers to the same agent. Concurrency is limited by the number of host interfaces sharing any particular agent interface. If a design requires higher data throughput, you can increase the number of host and agent interfaces to increase the number of transfers that occur simultaneously. The example below shows a system with three host interfaces.
Figure 116.  Avalon® Multiple Host Parallel AccessIn this Avalon® example, the DMA engine operates with Avalon® memory mapped read and write hosts. The yellow lines represent active simultaneous connections.
Figure 117. AXI Multiple Master Parallel AccessIn this example, the DMA engine operates with a single master, because in AXI, the write and read channels on the master are independent and can process transactions simultaneously. There is concurrency between the read and write channels, with the yellow lines representing concurrent datapaths.