Visible to Intel only — GUID: mwh1409958658039
Ixiasoft
Visible to Intel only — GUID: mwh1409958658039
Ixiasoft
1.14.5.1. Platform Designer Testbench Files
Platform Designer generates the following testbench files.
File Name or Directory Name |
Description |
---|---|
<system>_tb.qsys | The Platform Designer testbench system. |
<system>_tb.v or <system>_tb.vhd |
The top‑level testbench file that connects BFMs to the top‑level interfaces of <system>_tb.qsys. |
<system>_tb.spd | Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation and information about memory that you can initialize. |
<system>.html and <system>_tb.html |
A system report that contains connection information, a memory map showing the address of each agent with respect to each host to which it is connected, and parameter assignments. |
<system>_generation.rpt | Platform Designer generation log file. A summary of the messages that Platform Designer issues during testbench system generation. |
<system>.ipx | The IP Index File (.ipx) lists the available IP components, or a reference to other directories to search for IP components. |
<system>.svd | Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Platform Designer system. Similarly, during synthesis the .svd files for agent interfaces visible to System Console hosts are stored in the .sof file in the debug section. System Console reads this section, which Platform Designer can query for register map information. For system agents, Platform Designer can access the registers by name. |
mentor/ | Contains a ModelSim* script msim_setup.tcl to set up and run a simulation |
aldec/ | Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation. |
/synopsys/vcs /synopsys/vcsmx |
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS* MX simulation. |
/cadence | Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation. |
/xcelium | Contains a shell script xcelium_setup.sh and other setup files to set up and run an Xcelium* simulation. |
/common | Contains a set of Tcl files, <simulator>_files.tcl, which provide all design related simulation information required by a corresponding simulation script. The Tcl file contains designs from current system-level hierarchy, and references to sub-systems and IP components. |
/submodules | Contains HDL files for the submodule of the Platform Designer testbench system. |
<child IP cores>/ | For each generated child IP core directory, Platform Designer testbench generates /synth and /sim subdirectories. |