Visible to Intel only — GUID: mwh1409958828732
Ixiasoft
Visible to Intel only — GUID: mwh1409958828732
Ixiasoft
5. Platform Designer Interconnect
Platform Designer allows you to establish connections between Avalon® and AXI interfaces by generating an interconnect logic. This logic enables you to handle the protocol differences. Platform Designer creates the interconnect logic by converting all the protocols to a proprietary packet format. Then, the tool routes the packet through network switches to the appropriate AXI slaves or Avalon agents.5 Here, the packet converts to the slave's protocol.
Platform Designer supports Avalon® , AMBA* 3 AXI (version 1.0), AMBA* 4 AXI (version 2.0), AMBA* 4 AXI-Lite (version 2.0), AMBA* 4 AXI-Stream (version 1.0), and AMBA* 3 APB (version 1.0) interface specifications.
The video AMBA* AXI and Intel Avalon® Interoperation Using Platform Designer describes seamless integration of IP components using the AMBA* AXI and the Intel Avalon® interfaces.
Synchronous Reset Support
Platform Designer interconnect supports synchronous reset of registers in the interconnect. Use of synchronous reset can result in higher performance for Intel® Stratix® 10 designs because Intel® Stratix® 10 Hyper-Registers lack a reset signal. If a register in your Intel® Stratix® 10 design uses asynchronous reset, the Compiler cannot implement the register as a Hyper-Register, potentially reducing performance.
When Use synchronous reset is set to True in the Domains tab, all registers in the interconnect use synchronous reset. The Use synchronous reset option is enabled by default for Intel® Stratix® 10 devices, but is disabled by default for all other devices.
- Memory-Mapped Interfaces
- Avalon Streaming Interfaces
- Avalon Streaming Credit Interfaces
- Interrupt Interfaces
- Clock Interfaces
- Reset Interfaces
- Conduits
- Interconnect Pipelining
- Error Correction Coding (ECC) in Platform Designer Interconnect
- AMBA 3 AXI Protocol Specification Support (version 1.0)
- AMBA 3 APB Protocol Specification Support (version 1.0)
- AMBA 4 AXI Memory-Mapped Interface Support (version 2.0)
- AMBA 4 AXI Streaming Interface Support (version 1.0)
- AMBA 4 AXI-Lite Protocol Specification Support (version 2.0)
- Port Roles (Interface Signal Types)
- Platform Designer Interconnect Revision History