Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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Document Table of Contents

5. Platform Designer Interconnect

Platform Designer interconnect is a high-bandwidth structure that allows you to connect IP components to other IP components with various interfaces.

Platform Designer allows you to establish connections between Avalon® and AXI interfaces by generating an interconnect logic. This logic enables you to handle the protocol differences. Platform Designer creates the interconnect logic by converting all the protocols to a proprietary packet format. Then, the tool routes the packet through network switches to the appropriate AXI slaves or Avalon agents.5 Here, the packet converts to the slave's protocol.

Platform Designer supports Avalon® , AMBA* 3 AXI (version 1.0), AMBA* 4 AXI (version 2.0), AMBA* 4 AXI-Lite (version 2.0), AMBA* 4 AXI-Stream (version 1.0), and AMBA* 3 APB (version 1.0) interface specifications.

The video AMBA* AXI and Intel Avalon® Interoperation Using Platform Designer describes seamless integration of IP components using the AMBA* AXI and the Intel Avalon® interfaces.

Synchronous Reset Support

Platform Designer interconnect supports synchronous reset of registers in the interconnect. Use of synchronous reset can result in higher performance for Intel® Stratix® 10 designs because Intel® Stratix® 10 Hyper-Registers lack a reset signal. If a register in your Intel® Stratix® 10 design uses asynchronous reset, the Compiler cannot implement the register as a Hyper-Register, potentially reducing performance.

When Use synchronous reset is set to True in the Domains tab, all registers in the interconnect use synchronous reset. The Use synchronous reset option is enabled by default for Intel® Stratix® 10 devices, but is disabled by default for all other devices.

Note: In Platform Designer systems with no clock domain crossing, the initial reset requires asserting for at least 16 cycles. This action prevents the propagation of incorrect values that the reset tree skew may generate during the initial reset release, ensuring the resetting of all the Platform Designer components and interconnect. If system has multiple clocks, reset must be held high for at least 16 slowest clock cycles.
5 Platform Designer now replaces non-inclusive terms with "host" and "agent" inclusive terms for Avalon® memory mapped interface descriptions and related GUI elements.