Visible to Intel only — GUID: mwh1409958976764
Ixiasoft
Visible to Intel only — GUID: mwh1409958976764
Ixiasoft
5.8. Interconnect Pipelining
You can use pipeline stages within the interconnect to increase a design's fMAX. Insertion of pipeline stages reduces the combinational logic depth, while incurring additional latency and logic use.6
The Limit interconnect pipeline stages to option on the Domains tab allows you to specify the maximum number of fixed location Avalon® pipeline stages that Platform Designer can automatically insert in the command and response path, as Figure 195 illustrates. You can specify between 0 to 4 pipeline stages, where 0 means that the interconnect has a combinational datapath. Choosing 3 or 4 pipeline stages can significantly increase the logic utilization of the system. Limit interconnect pipeline stages to is specific to each Platform Designer system or subsystem.
If the Limit interconnect pipeline stages to setting does not provide enough fine control over the placement of pipelines, you can explicitly adjust the number of pipeline stages by clicking Show System with Interconnect on the Domains tab, as Add Pipeline Stages to the Interconnect Schematic describes.