Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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6.1.6.3. AXI Bridge Slave and Master Interface Parameters

Table 121.  AXI Bridge Slave and Master Interface Parameters
Parameter Description
ID Width

Controls the width of the thread ID of the master and slave interfaces.

Write/Read/Combined Acceptance Capability

Controls the depth of the FIFO that Platform Designer needs in the interconnect agents based on the maximum pending commands that the slave interface accepts.

Write/Read/Combined Issuing Capability

Controls the depth of the FIFO that Platform Designer needs in the interconnect agents based on the maximum pending commands that the master interface issues. Issuing capability must follow acceptance capability to avoid unnecessary creation of FIFOs in the bridge.

Note: Maximum acceptance/issuing capability is a model-only parameter and does not influence the bridge HDL. The bridge does not backpressure when this limit is reached. Downstream components or the interconnect must apply backpressure.