Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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4.5.3.1. Determining Effective Placement of Bridges

To determine the effective placement of a bridge, you should initially analyze each host in your system to determine if the connected agent devices support different bursting capabilities or operate in a different clock domain. The maximum burstcount of a component is visible as the burstcount signal in the HDL file of the component. The maximum burst length is 2 (width(burstcount -1)), therefore, if the burstcount width is four bits, the maximum burst length is eight. If no burstcount signal is present, the component does not support bursting or has a burst length of 1.

To determine if the system requires a clock crossing adapter between the host and agent interfaces, check the Clock column for the host and agent interfaces. If the clock is different for the host and agent interfaces, Platform Designer inserts a clock crossing adapter between them. To avoid creating multiple adapters, you can place the components containing agent interfaces behind a bridge so that Platform Designer creates a single adapter. By placing multiple components with the same burst or clock characteristics behind a bridge, you limit concurrency and the number of adapters.

You can also use a bridge to separate AXI and Avalon domains to minimize burst adaptation logic. For example, if there are multiple Avalon agents that are connected to an AXI master, you can consider inserting a bridge to access the adaptation logic once before the bridge, instead of once per agent. This implementation results in latency, and you would also lose concurrency between reads and writes.