Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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4.7.2. Minimizing Arbitration Logic by Consolidating Multiple Interfaces

As the number of components in a design increases, the amount of logic required to implement the interconnect also increases. The number of arbitration blocks increases for every agent interface that is shared by multiple host interfaces. The width of the read data multiplexer increases as the number of agent interfaces supporting read transfers increases on a per host interface basis. For these reasons, consider implementing multiple blocks of logic as a single interface to reduce interconnect logic utilization.