Visible to Intel only — GUID: mwh1409959068757
Ixiasoft
Visible to Intel only — GUID: mwh1409959068757
Ixiasoft
4.5.1.1. Inserting Pipeline Bridges
The Avalon® memory mapped pipeline bridge component integrates into any Platform Designer system. The pipeline bridge options can increase logic utilization and read latency. The change in topology may also reduce concurrency if multiple hosts arbitrate for the bridge. You can use the Avalon® memory mapped pipeline bridge to control topology without adding a pipeline stage. A pipeline bridge that does not add a pipeline stage is optimal in some latency-sensitive applications. For example, a CPU may benefit from minimal latency when accessing memory.