Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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6.6. Avalon® Streaming Delay Intel® FPGA IP

The Avalon® Streaming Delay Intel® FPGA IP provides a solution to delay Avalon® streaming transactions by a constant number of clock cycles. This IP supports up to 16 clock cycle delays.

Figure 231.  Avalon® Streaming Delay Intel® FPGA IP

The Avalon® Streaming Delay Intel® FPGA IP adds a delay between the input and output interfaces. The IP accepts transactions presented on the input interface and reproduces them on the output interface N cycles later without changing the transaction.

The input interface delays the input signals by a constant N number of clock cycles to the corresponding output signals of the output interface. The Number Of Delay Clocks parameter defines the constant N, which must be from 0 to 16. The change of the in_valid signal is reflected on the out_valid signal exactly N cycles later.