Visible to Intel only — GUID: mwh1409959275749
Ixiasoft
Visible to Intel only — GUID: mwh1409959275749
Ixiasoft
6.1.3. Avalon® Memory Mapped Pipeline Bridge Intel® FPGA IP
The Maximum pending read transactions parameter is the maximum number of pending reads that the Avalon® Memory Mapped bridge can queue up. To determine the best value for this parameter, review this same option for the bridge's connected agents and identify the highest value of the parameter, and then add the internal buffering requirements of the Avalon® Memory Mapped bridge. In general, the value is between 4 and 32. The limit for maximum queued transactions is 64.
You can use the Avalon® Memory Mapped bridge to export a single Avalon® memory mapped agent interface to control multiple Avalon® memory mapped agent devices. The pipelining feature is optional.
Because the agent interface is exported to the pins of the device, having a single agent port, rather than separate ports for each agent device, reduces the pin count of the FPGA. Refer to Interconnect Pipelining for more information.