Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.11. Creating Platform Designer Components Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2021.03.29 21.1
  • Converted to "host" and "agent" inclusive terminology for Avalon® memory mapped interface descriptions and related GUI elements throughout.
2020.12.14 20.4
  • Added new "Exporting HDL Parameters to a System" topic.
  • Added new "HDL Parameters Tab Settings and Controls" topic.
2020.09.28 20.3
  • Revised "Adding Generic Components to a System" to describes all implementations and refer to substeps for HDL and Blackbox parameters.
  • Revised "Adding Generic HDL Component Parameters" for latest steps and screenshot.
  • Added new "Adding Generic Blackbox Component Parameters" topic.
  • Added statement about AFFECTS_GENERATION to "Specify Parameters in the Platform Designer Component Editor" topic.
  • Reorganized the order of some topic to group similar items.
2020.05.01 20.1
  • Added note about .qar file requirements to "Design Guidelines for Component Instances" topic.
2020.04.06 18.1.0
  • Updated links and web page names in "Component Structure" and "Creating Platform Designer Components" topics.
2019.06.19 18.1.0
  • Added descriptions of AXI parameters in "Specify Parameters in the Platform Designer Component Editor."
2018.12.15 18.1.0
  • Replaced references to System Contents tab with new System View tab.
2018.05.07 18.0
  • Added scripting support for wire-level expressions.
2017.11.06 17.1.0
  • Changed instances of Qsys Pro to Platform Designer
  • Replaced mentions of altera_axi_default_slave to altera_error_response_slave
  • Added support for SystemVerilog interfaces with _hw.tcl.
  • Added support for user alterable HDL parameters with _hw.tcl.
  • Added support for High Level Synthesis file compilation.
2017.05.08 17.0.0
  • Updated Figure: Address Span Extender
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Implemented Qsys rebranding.
  • Added topics for Generic Component.
2015.11.02 15.1.0 Changed instances of Quartus II to Quartus Prime.
2015.05.04 15.0.0
  • Updated screen shots Files tab, Qsys Component Editor.
  • Added topic: Specify Interfaces and Signals in the Qsys Component Editor.
  • Added topic: Create an HDL File in the Qsys Component Editor.
  • Added topic: Create an HDL File Using a Template in the Qsys Component Editor.
November 2013 13.1.0
  • add_hdl_instance
  • Added Creating a Component With Differing Structural Qsys View and Generated Output Files.
May 2013 13.0.0
  • Consolidated content from other Qsys chapters.
  • Added Upgrading IP Components to the Latest Version.
  • Updated for AMBA APB support.
November 2012 12.1.0
  • Added AMBA AXI4 support.
  • Added the demo_axi_memory example with screen shots and example _hw.tcl code.
June 2012 12.0.0
  • Added new tab structure for the Component Editor.
  • Added AXI 3 support.
November 2011 11.1.0 Template update.
May 2011 11.0.0
  • Removed beta status.
  • Added Avalon Tri-state Conduit (Avalon‑TC) interface type.
  • Added many interface templates for Nios custom instructions and Avalon‑TC interfaces.
December 2010 10.1.0 Initial release.