Visible to Intel only — GUID: mwh1409958782920
Ixiasoft
Visible to Intel only — GUID: mwh1409958782920
Ixiasoft
3.3. Creating IP Components in the Component Editor
The Platform Designer Component Editor allows you to perform the following tasks:
- Specify component’s identifying information, such as name, version, author, etc.
- Specify the SystemVerilog, Verilog HDL, VHDL files, and constraint files that define the component for synthesis and simulation.
- Create an HDL template to define a component's interfaces, signals, and parameters.
- Set parameters on interfaces and signals that can alter the component's structure or functionality.
If you do not have a top-level HDL component file, you can use the Platform Designer Component Editor to add interfaces, signals, and parameters. In the Component Editor, the order in which the tabs appear reflects the recommended design flow for component development. You can use the Prev and Next buttons to guide you through the tabs.
In a Platform Designer system, the interfaces of a component are connected in the system, or exported as top-level signals from the system.
If the component is not based on an existing HDL file, enter the parameters, signals, and interfaces first, and then return to the Files tab to create the top-level HDL file template. When you click Finish, Platform Designer creates the component _hw.tcl file with the details that you enter in the Component Editor.
When you save the component, it appears in the IP Catalog.
Platform Designer Creates an _hw.tcl File from Entries in the Component Editor
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
add_interface_port reset reset_n reset_n Input 1
#
# connection point streaming
#
add_interface streaming avalon_streaming start
set_interface_property streaming associatedClock clock
set_interface_property streaming associatedReset reset
set_interface_property streaming dataBitsPerSymbol 8
set_interface_property streaming errorDescriptor ""
set_interface_property streaming firstSymbolInHighOrderBits true
set_interface_property streaming maxChannel 0
set_interface_property streaming readyLatency 0
set_interface_property streaming ENABLED true
add_interface_port streaming aso_data data Output 8
add_interface_port streaming aso_valid valid Output 1
add_interface_port streaming aso_ready ready Input 1
#
# connection point slave
#
add_interface slave axi end
set_interface_property slave associatedClock clock
set_interface_property slave associatedReset reset
set_interface_property slave readAcceptanceCapability 1
set_interface_property slave writeAcceptanceCapability 1
set_interface_property slave combinedAcceptanceCapability 1
set_interface_property slave readDataReorderingDepth 1
set_interface_property slave ENABLED true
add_interface_port slave axs_awid awid Input AXI_ID_W
...
add_interface_port slave axs_rresp rresp Output 2
- Save an IP Component and Create the _hw.tcl File
- Edit an IP Component with the Platform Designer Component Editor
- Specify IP Component Type Information
- Create an HDL File in the Platform Designer Component Editor
- Defining HDL Parameters in _hw.tcl
- Declaring SystemVerilog Interfaces in _hw.tcl
- Create an HDL File Using a Template in the Platform Designer Component Editor
- Specify Synthesis and Simulation Files in the Platform Designer Component Editor
- Add Signals and Interfaces in the Platform Designer Component Editor
- Specify Parameters in the Platform Designer Component Editor