Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

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ID 683609
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Creating a System with Platform Designer 2. Creating a Board Support Package with BSP Editor 3. Creating Platform Designer Components 4. Optimizing Platform Designer System Performance 5. Platform Designer Interconnect 6. Platform Designer System Design Components 7. Platform Designer Command-Line Utilities 8. Component Interface Tcl Reference 9. Intel® Quartus® Prime Pro Edition User Guide: Platform Designer Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
1. Creating a System with Platform Designer x
1.1. Platform Designer Interface Support 1.2. Platform Designer System Design Flow 1.3. Creating or Opening a Platform Designer System 1.4. Viewing a Platform Designer System 1.5. Adding IP Components to a System 1.6. Connecting System Components 1.7. Specifying Interconnect Parameters 1.8. Specifying Signal and Interface Boundary Requirements 1.9. Configuring Platform Designer System Security 1.10. Upgrading Outdated IP Components in Platform Designer 1.11. Synchronizing System Component Information 1.12. Validating System Integrity 1.13. Preserving a System Module, Interface, or Port for Debugging 1.14. Generating a Platform Designer System 1.15. Simulating Platform Designer Systems 1.16. Adding a System to an Intel® Quartus® Prime Project 1.17. Managing Hierarchical Platform Designer Systems 1.18. Saving and Archiving Platform Designer Systems 1.19. Comparing Platform Designer Systems and IP components 1.20. Running System Scripts 1.21. Creating a System with Platform Designer Revision History
1.3. Creating or Opening a Platform Designer System x
1.3.1. Specifying the Target Intel® FPGA Device for a System 1.3.2. Specifying Additional Application Memory 1.3.3. Synchronizing IP File References 1.3.4. Converting Incompatible Components
1.4. Viewing a Platform Designer System x
1.4.1. Viewing the System Hierarchy 1.4.2. Filtering the System View 1.4.3. Viewing System Connections 1.4.4. Viewing Clock and Reset Domains 1.4.5. Viewing Avalon® Memory-Mapped Domains in a System 1.4.6. Viewing the System Schematic 1.4.7. Customizing the Platform Designer Layout 1.4.8. Changing the Platform Designer Font
1.4.4. Viewing Clock and Reset Domains x
1.4.4.1. Viewing Clock Domains in a System 1.4.4.2. Viewing Reset Domains in a System
1.5. Adding IP Components to a System x
1.5.1. Modifying IP Parameters 1.5.2. Applying Preset Parameters for Specific Applications 1.5.3. Adding Third-Party IP Components 1.5.4. Specifying IP Component Instantiation Options 1.5.5. Creating or Opening an IP Core Variant
1.5.1. Modifying IP Parameters x
1.5.1.1. Viewing Component or Parameter Details 1.5.1.2. Viewing a Component's Block Symbol
1.5.2. Applying Preset Parameters for Specific Applications x
1.5.2.1. Creating IP Custom Preset Parameters Settings
1.5.3. Adding Third-Party IP Components x
1.5.3.1. IP Search Path Recursive Search 1.5.3.2. Defining the IP Search Path with Index Files
1.5.3.1. IP Search Path Recursive Search x
1.5.3.1.1. IP Search Path Precedence 1.5.3.1.2. IP Component Description Files
1.5.4. Specifying IP Component Instantiation Options x
1.5.4.1. Component Implementation Type Options
1.6. Connecting System Components x
1.6.1. Platform Designer 64-Bit Addressing Support 1.6.2. Connecting Hosts and Agents 1.6.3. Wire-Level Connectivity
1.6.1. Platform Designer 64-Bit Addressing Support x
1.6.1.1. Support for Avalon® Memory Mapped Non-Power of Two Data Widths
1.6.3. Wire-Level Connectivity x
1.6.3.1. Editing Wire-Level Expressions 1.6.3.2. Wire-Level Expression Syntax 1.6.3.3. Adding or Removing Ports from Wire-Level Endpoint Interfaces 1.6.3.4. Scripting Wire-Level Expressions
1.7. Specifying Interconnect Parameters x
1.7.1. Interconnect Parameters 1.7.2. Previewing the System Interconnect
1.8. Specifying Signal and Interface Boundary Requirements x
1.8.1. Interface Requirements Tab Fields 1.8.2. Editing Exported Interface Signal Names
1.9. Configuring Platform Designer System Security x
1.9.1. System Security Options 1.9.2. Specifying a Default Slave 1.9.3. Accessing Undefined Memory Regions
1.11. Synchronizing System Component Information x
1.11.1. System Info Tab Fields
1.12. Validating System Integrity x
1.12.1. Validating the System Integrity of Individual Components
1.14. Generating a Platform Designer System x
1.14.1. Generation Dialog Box Options 1.14.2. Specifying the Generation ID 1.14.3. Disabling or Enabling Parallel IP Generation 1.14.4. Files Generated for Platform Designer Systems 1.14.5. Generating System Testbench Files 1.14.6. Generating Example Designs for IP Components 1.14.7. Incremental System Generation Example 1.14.8. Generating the HPS IP Component System View Description File 1.14.9. Generating Header Files for Host Components
1.14.5. Generating System Testbench Files x
1.14.5.1. Platform Designer Testbench Files
1.15. Simulating Platform Designer Systems x
1.15.1. Adding Assertion Monitors for Simulation 1.15.2. Simulating Software Running on a Nios® II Processor
1.17. Managing Hierarchical Platform Designer Systems x
1.17.1. Adding a Subsystem to a Platform Designer System 1.17.2. Viewing and Traversing Subsystem Contents 1.17.3. Editing a Subsystem 1.17.4. Saving a Subsystem 1.17.5. Changing a Component's Hierarchy Level
1.18. Saving and Archiving Platform Designer Systems x
1.18.1. Saving Platform Designer Systems 1.18.2. Archiving Platform Designer Systems 1.18.3. Including Platform Designer Systems in Project Archives
1.18.3. Including Platform Designer Systems in Project Archives x
1.18.3.1. Project Files to Include In External Revision Control
1.19. Comparing Platform Designer Systems and IP components x
1.19.1. Using the System Diff Tool
2. Creating a Board Support Package with BSP Editor x
2.1. Creating a BSP from Platform Designer 2.2. Opening a BSP from Platform Designer 2.3. Saving a BSP from Platform Designer 2.4. Exporting a BSP as Tcl from Platform Designer 2.5. BSP Editor GUI 2.6. Creating a Board Support Package with BSP Editor Revision History
2.1. Creating a BSP from Platform Designer x
2.1.1. Create New BSP Dialog Box
2.5. BSP Editor GUI x
2.5.1. Main Tab 2.5.2. BSP Software Packages Tab 2.5.3. BSP Drivers Tab 2.5.4. BSP Linker Script Tab 2.5.5. BSP Enable File Generation Tab 2.5.6. BSP Target Directory Tab 2.5.7. Messages Tabs
2.5.4. BSP Linker Script Tab x
2.5.4.1. Linker Section Mappings 2.5.4.2. Linker Regions
3. Creating Platform Designer Components x
3.1. Platform Designer Components 3.2. Design Phases of an IP Component 3.3. Creating IP Components in the Component Editor 3.4. Creating Generic Components in a System 3.5. Exporting HDL Parameters to a System 3.6. Scripting Wire-Level Expressions 3.7. Control Interfaces Dynamically with an Elaboration Callback 3.8. Control File Generation Dynamically with Parameters and a Fileset Callback 3.9. Create a Composed Component or Subsystem 3.10. Add Component Instances to a Static or Generated Component 3.11. Creating Platform Designer Components Revision History
3.1. Platform Designer Components x
3.1.1. Platform Designer Interface Support 3.1.2. Component Structure 3.1.3. Component File Organization 3.1.4. Component Versions
3.1.4. Component Versions x
3.1.4.1. Upgrade IP Components to the Latest Version
3.3. Creating IP Components in the Component Editor x
3.3.1. Save an IP Component and Create the _hw.tcl File 3.3.2. Edit an IP Component with the Platform Designer Component Editor 3.3.3. Specify IP Component Type Information 3.3.4. Create an HDL File in the Platform Designer Component Editor 3.3.5. Defining HDL Parameters in _hw.tcl 3.3.6. Declaring SystemVerilog Interfaces in _hw.tcl 3.3.7. Create an HDL File Using a Template in the Platform Designer Component Editor 3.3.8. Specify Synthesis and Simulation Files in the Platform Designer Component Editor 3.3.9. Add Signals and Interfaces in the Platform Designer Component Editor 3.3.10. Specify Parameters in the Platform Designer Component Editor
3.3.8. Specify Synthesis and Simulation Files in the Platform Designer Component Editor x
3.3.8.1. Specify HDL Files for Synthesis in the Platform Designer Component Editor 3.3.8.2. Analyze Synthesis Files in the Platform Designer Component Editor 3.3.8.3. Name HDL Signals for Automatic Interface and Type Recognition in the Platform Designer Component Editor 3.3.8.4. Specify Files for Simulation in the Component Editor 3.3.8.5. Include an Internal Register Map Description in the .svd for Agent Interfaces Connected to an HPS Component
3.3.10. Specify Parameters in the Platform Designer Component Editor x
3.3.10.1. Valid Ranges for Parameters in the _hw.tcl File 3.3.10.2. Types of Platform Designer Parameters 3.3.10.3. Declare Parameters with Custom _hw.tcl Commands 3.3.10.4. Validate Parameter Values with a Validation Callback
3.3.10.2. Types of Platform Designer Parameters x
3.3.10.2.1. Platform Designer User Parameters 3.3.10.2.2. Platform Designer System Information Parameters 3.3.10.2.3. Platform Designer Derived Parameters
3.3.10.2.2. Platform Designer System Information Parameters x
3.3.10.2.2.1. Obtaining Device Trait Information Using PART_TRAIT System Information Parameter
3.3.10.2.3. Platform Designer Derived Parameters x
3.3.10.2.3.1. Parameterized Parameter Widths
3.4. Creating Generic Components in a System x
3.4.1. Adding Generic HDL Component Parameters 3.4.2. Adding Generic Blackbox Component Parameters 3.4.3. Adding Generic Component Interfaces and Signals 3.4.4. Adding Generic HLS Components 3.4.5. Creating a System Template for a Generic Component 3.4.6. Exporting a Generic Component
3.4.3. Adding Generic Component Interfaces and Signals x
3.4.3.1. Mirroring Interfaces in a Generic Component 3.4.3.2. Cloning Interfaces in a Generic Component 3.4.3.3. Importing Interfaces to a Generic Component
3.4.4. Adding Generic HLS Components x
3.4.4.1. Add High Level Synthesis Files to a Generic Component 3.4.4.2. Compile High Level Synthesis Files 3.4.4.3. Import High Level Synthesis Files
3.5. Exporting HDL Parameters to a System x
3.5.1. HDL Parameters Tab Settings and Controls
3.10. Add Component Instances to a Static or Generated Component x
3.10.1. Static IP Components 3.10.2. Generated Components 3.10.3. Design Guidelines for Adding Component Instances
4. Optimizing Platform Designer System Performance x
4.1. Designing with Avalon® and AXI Interfaces 4.2. Using Hierarchy in Systems 4.3. Using Concurrency in Memory-Mapped Systems 4.4. Inserting Pipeline Stages to Increase System Frequency 4.5. Using Bridges 4.6. Increasing Transfer Throughput 4.7. Reducing Logic Utilization 4.8. Reducing Power Consumption 4.9. Reset Polarity and Synchronization in Platform Designer 4.10. Optimizing Platform Designer System Performance Design Examples 4.11. Optimizing Platform Designer System Performance Revision History
4.1. Designing with Avalon® and AXI Interfaces x
4.1.1. Designing Streaming Components 4.1.2. Designing Memory-Mapped Components
4.3. Using Concurrency in Memory-Mapped Systems x
4.3.1. Implementing Concurrency With Multiple Hosts 4.3.2. Implementing Concurrency With Multiple Agents 4.3.3. Implementing Concurrency with DMA Engines
4.5. Using Bridges x
4.5.1. Using Bridges to Increase System Frequency 4.5.2. Using Bridges to Minimize Design Logic 4.5.3. Using Bridges to Minimize Adapter Logic 4.5.4. Considering the Effects of Using Bridges
4.5.1. Using Bridges to Increase System Frequency x
4.5.1.1. Inserting Pipeline Bridges 4.5.1.2. Using Clock Crossing Bridges
4.5.1.1. Inserting Pipeline Bridges x
4.5.1.1.1. Implementing Command Pipelining (Host-to-Agent) 4.5.1.1.2. Implementing Response Pipelining (Agent-to-Host)
4.5.2. Using Bridges to Minimize Design Logic x
4.5.2.1. Avoiding Speed Optimizations That Increase Logic 4.5.2.2. Limiting Concurrency
4.5.3. Using Bridges to Minimize Adapter Logic x
4.5.3.1. Determining Effective Placement of Bridges 4.5.3.2. Changing the Response Buffer Depth
4.5.4. Considering the Effects of Using Bridges x
4.5.4.1. Increased Latency 4.5.4.2. Limited Concurrency 4.5.4.3. Address Space Translation 4.5.4.4. Address Coherency
4.5.4.1. Increased Latency x
4.5.4.1.1. Acceptable Latency Increase 4.5.4.1.2. Unacceptable Latency Increase
4.6. Increasing Transfer Throughput x
4.6.1. Using Pipelined Transfers 4.6.2. Arbitration Shares and Bursts
4.6.1. Using Pipelined Transfers x
4.6.1.1. Using the Maximum Pending Reads Parameter
4.6.2. Arbitration Shares and Bursts x
4.6.2.1. Differences Between Arbitration Shares and Bursts 4.6.2.2. Choosing Avalon® Memory Mapped Interface Types 4.6.2.3. Avalon® Memory Mapped Burst Host Example
4.6.2.2. Choosing Avalon® Memory Mapped Interface Types x
4.6.2.2.1. Simple Avalon® Memory Mapped Interfaces 4.6.2.2.2. Pipelined Avalon® Memory Mapped Interfaces 4.6.2.2.3. Burst Avalon® Memory Mapped Interfaces
4.7. Reducing Logic Utilization x
4.7.1. Minimizing Interconnect Logic to Reduce Logic Unitization 4.7.2. Minimizing Arbitration Logic by Consolidating Multiple Interfaces 4.7.3. Reducing Logic Utilization With Multiple Clock Domains 4.7.4. Duration of Transfers Crossing Clock Domains
4.7.1. Minimizing Interconnect Logic to Reduce Logic Unitization x
4.7.1.1. Creating Dedicated Host and Agent Connections to Minimize Interconnect Logic 4.7.1.2. Removing Unnecessary Connections to Minimize Interconnect Logic 4.7.1.3. Simplifying Address Decode Logic
4.7.2. Minimizing Arbitration Logic by Consolidating Multiple Interfaces x
4.7.2.1. Logic Consolidation Trade-Offs 4.7.2.2. Consolidating Interfaces
4.8. Reducing Power Consumption x
4.8.1. Reducing Power Consumption With Multiple Clock Domains 4.8.2. Reducing Power Consumption by Minimizing Toggle Rates 4.8.3. Reducing Power Consumption by Disabling Logic
4.10. Optimizing Platform Designer System Performance Design Examples x
4.10.1. Avalon Pipelined Read Host Example 4.10.2. Multiplexer Examples
4.10.1. Avalon Pipelined Read Host Example x
4.10.1.1. Avalon Pipelined Read Host Example Design Requirements 4.10.1.2. Expected Throughput Improvement
5. Platform Designer Interconnect x
5.1. Memory-Mapped Interfaces 5.2. Avalon® Streaming Interfaces 5.3. Avalon® Streaming Credit Interfaces 5.4. Interrupt Interfaces 5.5. Clock Interfaces 5.6. Reset Interfaces 5.7. Conduits 5.8. Interconnect Pipelining 5.9. Error Correction Coding (ECC) in Platform Designer Interconnect 5.10. AMBA* 3 AXI Protocol Specification Support (version 1.0) 5.11. AMBA* 3 APB Protocol Specification Support (version 1.0) 5.12. AMBA* 4 AXI Memory-Mapped Interface Support (version 2.0) 5.13. AMBA* 4 AXI Streaming Interface Support (version 1.0) 5.14. AMBA* 4 AXI-Lite Protocol Specification Support (version 2.0) 5.15. Port Roles (Interface Signal Types) 5.16. Platform Designer Interconnect Revision History
5.1. Memory-Mapped Interfaces x
5.1.1. Platform Designer Packet Format 5.1.2. Interconnect Domains 5.1.3. Host Network Interfaces 5.1.4. Agent Network Interfaces 5.1.5. Arbitration 5.1.6. Memory-Mapped Arbiter 5.1.7. Datapath Multiplexing Logic 5.1.8. Width Adaptation 5.1.9. Burst Adapter 5.1.10. Waitrequest Allowance Adapter 5.1.11. Read and Write Responses 5.1.12. Platform Designer Address Decoding
5.1.1. Platform Designer Packet Format x
5.1.1.1. Fields in the Platform Designer Packet Format 5.1.1.2. Transaction Types for Memory-Mapped Interfaces 5.1.1.3. Platform Designer Transformations
5.1.2. Interconnect Domains x
5.1.2.1. Using One Domain with Width Adaptation 5.1.2.2. Using Two Separate Domains
5.1.3. Host Network Interfaces x
5.1.3.1. Avalon® Memory Mapped Host Agent 5.1.3.2. Avalon® Memory Mapped Host Translator 5.1.3.3. AXI Master Agent 5.1.3.4. AXI Translator 5.1.3.5. APB Master Agent 5.1.3.6. APB Slave Agent 5.1.3.7. APB Translator 5.1.3.8. AHB Slave Agent 5.1.3.9. Memory-Mapped Router 5.1.3.10. Memory-Mapped Traffic Limiter
5.1.4. Agent Network Interfaces x
5.1.4.1. Avalon® Memory Mapped Agent Translator 5.1.4.2. AXI Translator 5.1.4.3. Wait State Insertion 5.1.4.4. Avalon® Memory Mapped Agent Component 5.1.4.5. AXI Slave Agent
5.1.5. Arbitration x
5.1.5.1. Round-Robin Arbitration 5.1.5.2. Fixed Priority Arbitration
5.1.5.1. Round-Robin Arbitration x
5.1.5.1.1. Fairness-Based Shares 5.1.5.1.2. Round-Robin Scheduling
5.1.5.2. Fixed Priority Arbitration x
5.1.5.2.1. Designate a Platform Designer Agent to Use Fixed Priority Arbitration 5.1.5.2.2. Fixed Priority Arbitration with AXI Masters and Avalon® Memory Mapped Agents
5.1.8. Width Adaptation x
5.1.8.1. Memory-Mapped Width Adapter
5.1.8.1. Memory-Mapped Width Adapter x
5.1.8.1.1. AXI Wide-to-Narrow Adaptation 5.1.8.1.2. AXI Narrow-to-Wide Adaptation
5.1.9. Burst Adapter x
5.1.9.1. Burst Adapter Implementation Options 5.1.9.2. Burst Adaptation: AXI to Avalon® 5.1.9.3. Burst Adaptation: Avalon® to AXI
5.2. Avalon® Streaming Interfaces x
5.2.1. Avalon® Streaming Adapters
5.2.1. Avalon® Streaming Adapters x
5.2.1.1. Avalon® Streaming Adapter 5.2.1.2. Channel Adapter 5.2.1.3. Data Format Adapter 5.2.1.4. Error Adapter 5.2.1.5. Timing Adapter
5.2.1.1. Avalon® Streaming Adapter x
5.2.1.1.1. Avalon® Streaming Adapter Parameters Common to Source and Sink Interfaces 5.2.1.1.2. Avalon® Streaming Adapter Upstream Source Interface Parameters 5.2.1.1.3. Avalon® Streaming Adapter Downstream Sink Interface Parameters
5.2.1.2. Channel Adapter x
5.2.1.2.1. Avalon® Streaming Channel Adapter Input Interface Parameters 5.2.1.2.2. Avalon® Streaming Channel Adapter Output Interface Parameters 5.2.1.2.3. Avalon® Streaming Channel Adapter Common to Input and Output Interface Parameters
5.2.1.3. Data Format Adapter x
5.2.1.3.1. Avalon® Streaming Data Format Adapter Input Interface Parameters 5.2.1.3.2. Avalon® Streaming Data Format Adapter Output Interface Parameters 5.2.1.3.3. Avalon® Streaming Data Format Adapter Common to Input and Output Interface Parameters
5.2.1.4. Error Adapter x
5.2.1.4.1. Avalon® Streaming Error Adapter Input Interface Parameters 5.2.1.4.2. Avalon® Streaming Error Adapter Output Interface Parameters 5.2.1.4.3. Avalon® Streaming Error Adapter Common to Input and Output Interface Parameters
5.2.1.5. Timing Adapter x
5.2.1.5.1. Avalon® Streaming Timing Adapter Input Interface Parameters 5.2.1.5.2. Avalon® Streaming Timing Adapter Output Interface Parameters 5.2.1.5.3. Avalon® Streaming Timing Adapter Common to Input and Output Interface Parameters
5.3. Avalon® Streaming Credit Interfaces x
5.3.1. Terms and Concepts 5.3.2. Avalon® Streaming Credit Adapters 5.3.3. Avalon® Streaming Credit Multiplexer 5.3.4. Avalon® Streaming Credit Demultiplexer 5.3.5. Avalon® Streaming Credit Pipeline Bridge
5.3.2. Avalon® Streaming Credit Adapters x
5.3.2.1. Avalon® Streaming Credit Wide to Narrow Adapter 5.3.2.2. Avalon® Streaming Credit Narrow to Wide Adapter 5.3.2.3. Avalon® Streaming Credit Max Credit Adapter 5.3.2.4. Avalon® Streaming Ready to Credit Adapter 5.3.2.5. Avalon® Streaming Credit to Ready Adapter
5.3.2.1. Avalon® Streaming Credit Wide to Narrow Adapter x
5.3.2.1.1. Avalon® Streaming Credit Wide to Narrow Adapter Interface Parameters 5.3.2.1.2. Avalon® Streaming Credit Wide to Narrow Adapter Interface Signals
5.3.2.2. Avalon® Streaming Credit Narrow to Wide Adapter x
5.3.2.2.1. Avalon® Streaming Credit Narrow to Wide Adapter Interface Parameters 5.3.2.2.2. Avalon® Streaming Credit Narrow to Wide Adapter Interface Signals
5.3.2.3. Avalon® Streaming Credit Max Credit Adapter x
5.3.2.3.1. Avalon® Streaming Credit Max Credit Adapter Interface Parameters 5.3.2.3.2. Avalon® Streaming Credit Max Credit Adapter Interface Signals
5.3.2.4. Avalon® Streaming Ready to Credit Adapter x
5.3.2.4.1. Avalon® Streaming Ready to Credit Adapter Interface Parameters 5.3.2.4.2. Avalon® Streaming Ready to Credit Adapter Interface Signals
5.3.2.5. Avalon® Streaming Credit to Ready Adapter x
5.3.2.5.1. Avalon® Streaming Credit to Ready Adapter Interface Parameters 5.3.2.5.2. Avalon® Streaming Credit to Ready Adapter Interface Signals
5.3.3. Avalon® Streaming Credit Multiplexer x
5.3.3.1. Avalon® Streaming Credit Multiplexer Parameters 5.3.3.2. Avalon® Streaming Credit Multiplexer Interface Signals
5.3.4. Avalon® Streaming Credit Demultiplexer x
5.3.4.1. Avalon® Streaming Credit Demultiplexer Parameters 5.3.4.2. Avalon® Streaming Credit Demultiplexer Interface Signals
5.3.5. Avalon® Streaming Credit Pipeline Bridge x
5.3.5.1. Avalon® Streaming Credit Pipeline Bridge Parameters 5.3.5.2. Avalon® Streaming Credit Pipeline Bridge Interface Signals
5.4. Interrupt Interfaces x
5.4.1. Individual Requests IRQ Scheme 5.4.2. Assigning IRQs in Platform Designer
5.4.2. Assigning IRQs in Platform Designer x
5.4.2.1. IRQ Bridge 5.4.2.2. IRQ Mapper 5.4.2.3. IRQ Clock Crosser
5.5. Clock Interfaces x
5.5.1. (High Speed Serial Interface) HSSI Clock Interfaces
5.5.1. (High Speed Serial Interface) HSSI Clock Interfaces x
5.5.1.1. HSSI Serial Clock Interface 5.5.1.2. HSSI Bonded Clock Interface
5.5.1.1. HSSI Serial Clock Interface x
5.5.1.1.1. HSSI Serial Clock Source 5.5.1.1.2. HSSI Serial Clock Sink 5.5.1.1.3. HSSI Serial Clock Connection 5.5.1.1.4. HSSI Serial Clock Example
5.5.1.2. HSSI Bonded Clock Interface x
5.5.1.2.1. HSSI Bonded Clock Source 5.5.1.2.2. HSSI Bonded Clock Sink 5.5.1.2.3. HSSI Bonded Clock Connection 5.5.1.2.4. HSSI Bonded Clock Example
5.6. Reset Interfaces x
5.6.1. Single Global Reset Signal Implemented by Platform Designer 5.6.2. Reset Controller 5.6.3. Reset Bridge 5.6.4. Reset Sequencer
5.6.4. Reset Sequencer x
5.6.4.1. Reset Sequencer Parameters 5.6.4.2. Reset Sequencer Timing Diagrams 5.6.4.3. Reset Sequencer CSR Registers 5.6.4.4. Reset Sequencer Software Flows
5.6.4.3. Reset Sequencer CSR Registers x
5.6.4.3.1. Reset Sequencer Status Register 5.6.4.3.2. Reset Sequencer Interrupt Enable Register 5.6.4.3.3. Reset Sequencer Control Register 5.6.4.3.4. Reset Sequencer Software Sequenced Reset Assert Control Register 5.6.4.3.5. Reset Sequencer Software Sequenced Reset Deassert Control Register 5.6.4.3.6. Reset Sequencer Software Direct Controlled Resets 5.6.4.3.7. Reset Sequencer Software Reset Masking
5.6.4.4. Reset Sequencer Software Flows x
5.6.4.4.1. Reset Sequencer (Software-Triggered) Flow 5.6.4.4.2. Reset Assert Flow 5.6.4.4.3. Reset Deassert Flow 5.6.4.4.4. Reset Assert (Software Sequenced) Flow 5.6.4.4.5. Reset Deassert (Software Sequenced) Flow
5.8. Interconnect Pipelining x
5.8.1. Add Pipeline Stages to the Interconnect Schematic
5.10. AMBA* 3 AXI Protocol Specification Support (version 1.0) x
5.10.1. Channels 5.10.2. Cache Support 5.10.3. Security Support 5.10.4. Atomic Accesses 5.10.5. Response Signaling 5.10.6. Ordering Model 5.10.7. Data Buses 5.10.8. Unaligned Address Commands 5.10.9. Avalon® and AXI Transaction Support
5.10.1. Channels x
5.10.1.1. Read and Write Address Channels 5.10.1.2. Write Data, Write Response, and Read Data Channels 5.10.1.3. Low Power Channel
5.10.2. Cache Support x
5.10.2.1. Bufferable 5.10.2.2. Cacheable (Modifiable)
5.10.6. Ordering Model x
5.10.6.1. AXI and Avalon® Ordering
5.10.9. Avalon® and AXI Transaction Support x
5.10.9.1. Transaction Cannot Cross 4KB Boundaries 5.10.9.2. Adjacent Bytelanes with Partial Width Transactions 5.10.9.3. Handling Read Side Effects
5.11. AMBA* 3 APB Protocol Specification Support (version 1.0) x
5.11.1. Bridges 5.11.2. Burst Adaptation 5.11.3. Width Adaptation 5.11.4. Error Response
5.12. AMBA* 4 AXI Memory-Mapped Interface Support (version 2.0) x
5.12.1. Burst Support 5.12.2. QoS 5.12.3. Regions 5.12.4. Write Response Dependency 5.12.5. AWCACHE and ARCACHE 5.12.6. Width Adaptation and Data Packing in Platform Designer 5.12.7. Ordering Model 5.12.8. Read and Write Allocate 5.12.9. Locked Transactions 5.12.10. Memory Types 5.12.11. Mismatched Attributes 5.12.12. Signals
5.13. AMBA* 4 AXI Streaming Interface Support (version 1.0) x
5.13.1. Connection Points 5.13.2. Adaptation
5.13.1. Connection Points x
5.13.1.1. AMBA* 4 AXI Streaming Connection Point Parameters 5.13.1.2. AMBA* 4 AXI Streaming Connection Point Signals
5.14. AMBA* 4 AXI-Lite Protocol Specification Support (version 2.0) x
5.14.1. AMBA* 4 AXI-Lite Signals 5.14.2. AMBA* 4 AXI-Lite Bus Width 5.14.3. AMBA* 4 AXI-Lite Outstanding Transactions 5.14.4. AMBA* 4 AXI-Lite IDs 5.14.5. Connections Between AMBA* 3 AXI, AMBA* 4 AXI and AMBA* 4 AXI-Lite 5.14.6. AMBA* 4 AXI-Lite Response Merging
5.14.5. Connections Between AMBA* 3 AXI, AMBA* 4 AXI and AMBA* 4 AXI-Lite x
5.14.5.1. AMBA* 4 AXI-Lite Slave Requirements 5.14.5.2. AMBA* 4 AXI-Lite Data Packing
5.15. Port Roles (Interface Signal Types) x
5.15.1. AXI Master Interface Signal Types 5.15.2. AXI Slave Interface Signal Types 5.15.3. AMBA* 4 AXI Master Interface Signal Types 5.15.4. AMBA* 4 AXI Slave Interface Signal Types 5.15.5. AMBA* 4 AXI-Stream Master and Slave Interface Signal Types 5.15.6. AMBA* 4 AXI-Lite Signal Support and Limitations 5.15.7. APB Interface Signal Types 5.15.8. Avalon® Memory Mapped Interface Signal Roles 5.15.9. Avalon® Streaming Interface Signal Roles 5.15.10. Avalon® Streaming Credit Interface Signal Roles 5.15.11. Avalon® Streaming Credit User Signals 5.15.12. Avalon® Clock Source Signal Roles 5.15.13. Avalon® Clock Sink Signal Roles 5.15.14. Avalon® Conduit Signal Roles 5.15.15. Avalon® Tristate Conduit Signal Roles 5.15.16. Avalon® Tri-State Agent Interface Signal Types 5.15.17. Avalon® Interrupt Sender Signal Roles 5.15.18. Avalon® Interrupt Receiver Signal Roles
5.15.6. AMBA* 4 AXI-Lite Signal Support and Limitations x
5.15.6.1. ACE-Lite Transaction Support and Limitations
5.15.10. Avalon® Streaming Credit Interface Signal Roles x
5.15.10.1. Synchronous Interface 5.15.10.2. Typical Data Transfers 5.15.10.3. Returning the Credits
5.15.11. Avalon® Streaming Credit User Signals x
5.15.11.1. Per-Symbol User Signal 5.15.11.2. Per-Packet User Signal
6. Platform Designer System Design Components x
6.1. Bridges 6.2. Error Response Slave Intel® FPGA IP 6.3. Tri-State Components 6.4. Avalon® Data Pattern Generator and Checker Intel® FPGA IP 6.5. Avalon® Streaming Splitter Intel® FPGA IP 6.6. Avalon® Streaming Delay Intel® FPGA IP 6.7. Avalon® Streaming Round Robin Scheduler Intel® FPGA IP 6.8. Avalon® Packets to Transactions Converter Intel® FPGA IP 6.9. Avalon® Streaming Pipeline Stage Intel® FPGA IP 6.10. Avalon® Streaming Multiplexer and Demultiplexer Intel® FPGA IP 6.11. Avalon® Streaming Single-Clock and Dual-Clock FIFO Intel® FPGA IP 6.12. Platform Designer System Design Components Revision History
6.1. Bridges x
6.1.1. Clock Bridge Intel® FPGA IP 6.1.2. Avalon® Memory Mapped Clock Crossing Bridge Intel® FPGA IP 6.1.3. Avalon® Memory Mapped Pipeline Bridge Intel® FPGA IP 6.1.4. Avalon® Memory Mapped Unaligned Burst Expansion Bridge Intel® FPGA IP 6.1.5. Bridges Between Avalon® and AXI Interfaces 6.1.6. AXI Bridge Intel® FPGA IP 6.1.7. AXI Timeout Bridge Intel® FPGA IP 6.1.8. Address Span Extender Intel® FPGA IP
6.1.2. Avalon® Memory Mapped Clock Crossing Bridge Intel® FPGA IP x
6.1.2.1. Avalon® Memory Mapped Clock Crossing Bridge Example 6.1.2.2. Avalon® Memory Mapped Clock Crossing Bridge Parameters
6.1.4. Avalon® Memory Mapped Unaligned Burst Expansion Bridge Intel® FPGA IP x
6.1.4.1. Using the Avalon® Memory Mapped Unaligned Burst Expansion Bridge 6.1.4.2. Avalon® Memory Mapped Unaligned Burst Expansion Bridge Parameters 6.1.4.3. Avalon® Memory Mapped Unaligned Burst Expansion Bridge Example
6.1.6. AXI Bridge Intel® FPGA IP x
6.1.6.1. AXI Bridge Signal Types 6.1.6.2. AXI Bridge Parameters 6.1.6.3. AXI Bridge Slave and Master Interface Parameters
6.1.7. AXI Timeout Bridge Intel® FPGA IP x
6.1.7.1. AXI Timeout Bridge Stages 6.1.7.2. AXI Timeout Bridge Parameters
6.1.8. Address Span Extender Intel® FPGA IP x
6.1.8.1. CTRL Register Layout 6.1.8.2. Address Span Extender Parameters 6.1.8.3. Calculating the Address Span Extender Agent Address 6.1.8.4. Using the Address Span Extender 6.1.8.5. Alternate Options for the Address Span Extender 6.1.8.6. Nios® II Support
6.2. Error Response Slave Intel® FPGA IP x
6.2.1. Error Response Slave Parameters 6.2.2. Error Response Slave CSR Registers 6.2.3. Designating a Default Agent
6.2.2. Error Response Slave CSR Registers x
6.2.2.1. Error Response Slave Access Violation Service 6.2.2.2. CSR Interrupt Status Registers 6.2.2.3. CSR Read Access Violation Log Registers 6.2.2.4. CSR Write Access Violation Log Registers
6.3. Tri-State Components x
6.3.1. Generic Tri-State Controller Intel® FPGA IP 6.3.2. Tri-State Conduit Pin Sharer Intel® FPGA IP 6.3.3. Tri-State Conduit Bridge Intel® FPGA IP
6.4. Avalon® Data Pattern Generator and Checker Intel® FPGA IP x
6.4.1. Avalon® Data Pattern Generator Intel® FPGA IP 6.4.2. Avalon® Data Pattern Checker Intel® FPGA IP 6.4.3. Avalon® Data Pattern Generator and Checker IP Software Programming Model 6.4.4. Avalon® Data Pattern Generator IP API 6.4.5. Avalon® Data Pattern Checker IP API
6.4.1. Avalon® Data Pattern Generator Intel® FPGA IP x
6.4.1.1. Avalon® Data Pattern Generator IP Command Interface 6.4.1.2. Avalon® Data Pattern Generator IP Control and Status Interface 6.4.1.3. Avalon® Data Pattern Generator IP Output Interface 6.4.1.4. Avalon® Data Pattern Generator IP Functional Parameter
6.4.2. Avalon® Data Pattern Checker Intel® FPGA IP x
6.4.2.1. Avalon® Data Pattern Checker IP Input Interface 6.4.2.2. Avalon® Data Pattern Checker IP Control and Status Interface 6.4.2.3. Avalon® Data Pattern Checker IP Functional Parameter 6.4.2.4. Avalon® Data Pattern Checker Input Parameters
6.4.3. Avalon® Data Pattern Generator and Checker IP Software Programming Model x
6.4.3.1. HAL System Library Support 6.4.3.2. Avalon® Data Pattern Generator and Checker IP Files 6.4.3.3. Avalon® Data Pattern Generator and Checker IP Register Maps
6.4.3.3. Avalon® Data Pattern Generator and Checker IP Register Maps x
6.4.3.3.1. Avalon® Data Pattern Generator IP Control and Status Registers 6.4.3.3.2. Avalon® Data Pattern Generator IP Command Registers 6.4.3.3.3. Avalon® Data Pattern Checker IP Control and Status Registers
6.4.4. Avalon® Data Pattern Generator IP API x
6.4.4.1. data_source_reset() 6.4.4.2. data_source_init() 6.4.4.3. data_source_get_id() 6.4.4.4. data_source_get_supports_packets() 6.4.4.5. data_source_get_num_channels() 6.4.4.6. data_source_get_symbols_per_cycle() 6.4.4.7. data_source_get_enable() 6.4.4.8. data_source_set_enable() 6.4.4.9. data_source_get_throttle() 6.4.4.10. data_source_set_throttle() 6.4.4.11. data_source_is_busy() 6.4.4.12. data_source_fill_level() 6.4.4.13. data_source_send_data()
6.4.5. Avalon® Data Pattern Checker IP API x
6.4.5.1. data_sink_reset() 6.4.5.2. data_sink_init() 6.4.5.3. data_sink_get_id() 6.4.5.4. data_sink_get_supports_packets() 6.4.5.5. data_sink_get_num_channels() 6.4.5.6. data_sink_get_symbols_per_cycle() 6.4.5.7. data_sink_get_enable() 6.4.5.8. data_sink_set enable() 6.4.5.9. data_sink_get_throttle() 6.4.5.10. data_sink_set_throttle() 6.4.5.11. data_sink_get_packet_count() 6.4.5.12. data_sink_get_error_count() 6.4.5.13. data_sink_get_symbol_count() 6.4.5.14. data_sink_get_exception() 6.4.5.15. data_sink_exception_is_exception() 6.4.5.16. data_sink_exception_has_data_error() 6.4.5.17. data_sink_exception_has_missing_sop() 6.4.5.18. data_sink_exception_has_missing_eop() 6.4.5.19. data_sink_exception_signalled_error() 6.4.5.20. data_sink_exception_channel()
6.5. Avalon® Streaming Splitter Intel® FPGA IP x
6.5.1. Avalon® Streaming Splitter Intel® FPGA IP Backpressure 6.5.2. Avalon® Streaming Splitter Intel® FPGA IP Interfaces 6.5.3. Avalon® Streaming Splitter Intel® FPGA IP Parameters
6.6. Avalon® Streaming Delay Intel® FPGA IP x
6.6.1. Avalon® Streaming Delay Intel® FPGA IP Reset Signal 6.6.2. Avalon® Streaming Delay Intel® FPGA IP Interfaces 6.6.3. Avalon® Streaming Delay Intel® FPGA IP Parameters
6.7. Avalon® Streaming Round Robin Scheduler Intel® FPGA IP x
6.7.1. Avalon® Streaming Round Robin Scheduler IP Almost-Full Status Interface 6.7.2. Avalon® Streaming Round Robin Scheduler IP Request Interface 6.7.3. Avalon® Streaming Round Robin Scheduler IP Operation 6.7.4. Avalon® Streaming Round Robin Scheduler IP Parameters
6.8. Avalon® Packets to Transactions Converter Intel® FPGA IP x
6.8.1. Avalon® Packets to Transactions Converter IP Interfaces 6.8.2. Avalon® Packets to Transactions Converter IP Operation
6.8.2. Avalon® Packets to Transactions Converter IP Operation x
6.8.2.1. Avalon® Packets to Transactions Converter IP Data Packet Formats 6.8.2.2. Avalon® Packets to Transactions Converter IP Supported Transactions 6.8.2.3. Avalon® Packets to Transactions IP Converter Malformed Packets
6.10. Avalon® Streaming Multiplexer and Demultiplexer Intel® FPGA IP x
6.10.1. Avalon® Streaming Multiplexer and Demultiplexer Software Programming Model 6.10.2. Avalon® Streaming Multiplexer Intel® FPGA IP 6.10.3. Avalon® Streaming Demultiplexer Intel® FPGA IP
6.10.2. Avalon® Streaming Multiplexer Intel® FPGA IP x
6.10.2.1. Avalon® Streaming Multiplexer IP Input Interfaces 6.10.2.2. Avalon® Multiplexer IP Output Interface 6.10.2.3. Avalon® Multiplexer IP Parameters
6.10.3. Avalon® Streaming Demultiplexer Intel® FPGA IP x
6.10.3.1. Avalon® Streaming Demultiplexer IP Input Interface 6.10.3.2. Avalon® Streaming Demultiplexer IP Output Interface 6.10.3.3. Avalon® Streaming Demultiplexer IP Parameters
6.11. Avalon® Streaming Single-Clock and Dual-Clock FIFO Intel® FPGA IP x
6.11.1. Interfaces Implemented in FIFO Cores 6.11.2. Avalon® Streaming FIFO IP Operating Modes 6.11.3. Avalon® Streaming FIFO IP Buffer Fill Level 6.11.4. Almost-Full and Almost-Empty Thresholds to Prevent Overflow and Underflow 6.11.5. Avalon® Streaming Single-Clock and Dual-Clock FIFO IP Parameters 6.11.6. Avalon® Streaming Single-Clock FIFO IP Registers
6.11.1. Interfaces Implemented in FIFO Cores x
6.11.1.1. Avalon® Streaming Data Interface 6.11.1.2. Avalon® Memory Mapped Control and Status Register Interface 6.11.1.3. Avalon® Streaming Status Interface
7. Platform Designer Command-Line Utilities x
7.1. Run the Platform Designer Editor with qsys-edit 7.2. Scripting IP Core Generation 7.3. Display Available IP Components with ip-catalog 7.4. Create an .ipx File with ip-make-ipx 7.5. Generate Simulation Scripts 7.6. Generate a Platform Designer System with qsys-script 7.7. Parameterizing an Instantiated IP Core after save_system Command 7.8. Validate the Generic Components in a System with qsys-validate 7.9. Generate an IP Component or Platform Designer System with quartus_ipgenerate 7.10. Generate an IP Variation File with ip-deploy 7.11. Archive and Extract Platform Designer Systems with qsys-archive 7.12. Platform Designer Scripting Command Reference 7.13. Platform Designer Scripting Property Reference 7.14. Platform Designer Command-Line Interface Revision History
7.2. Scripting IP Core Generation x
7.2.1. qsys-generate Command-Line Options
7.12. Platform Designer Scripting Command Reference x
7.12.1. System 7.12.2. Subsystems 7.12.3. Domains and Interfaces 7.12.4. Instances 7.12.5. Instantiations 7.12.6. Components 7.12.7. Connections 7.12.8. Top-level Exports 7.12.9. Validation 7.12.10. Miscellaneous 7.12.11. Wire-Level Connection Commands
7.12.1. System x
7.12.1.1. create_system 7.12.1.2. export_hw_tcl 7.12.1.3. get_device_families 7.12.1.4. get_devices 7.12.1.5. get_module_properties 7.12.1.6. get_module_property 7.12.1.7. get_project_properties 7.12.1.8. get_project_property 7.12.1.9. load_system 7.12.1.10. save_system 7.12.1.11. set_design_id 7.12.1.12. set_module_property 7.12.1.13. set_project_property
7.12.2. Subsystems x
7.12.2.1. get_composed_connections 7.12.2.2. get_composed_connection_parameter_value 7.12.2.3. get_composed_connection_parameters 7.12.2.4. get_composed_instance_assignment 7.12.2.5. get_composed_instance_assignments 7.12.2.6. get_composed_instance_parameter_value 7.12.2.7. get_composed_instance_parameters 7.12.2.8. get_composed_instances
7.12.3. Domains and Interfaces x
7.12.3.1. set_domain_assignment 7.12.3.2. get_domain_assignment 7.12.3.3. get_domain_assignments 7.12.3.4. set_interface_assignment 7.12.3.5. get_interface_assignment 7.12.3.6. get_interface_assignments 7.12.3.7. set_postadaptation_assignment 7.12.3.8. get_postadaptation_assignment 7.12.3.9. get_postadaptation_assignments
7.12.4. Instances x
7.12.4.1. add_instance 7.12.4.2. apply_instance_preset 7.12.4.3. create_ip 7.12.4.4. add_component 7.12.4.5. duplicate_instance 7.12.4.6. enable_instance_parameter_update_callback 7.12.4.7. get_instance_assignment 7.12.4.8. get_instance_assignments 7.12.4.9. get_instance_documentation_links 7.12.4.10. get_instance_interface_assignment 7.12.4.11. get_instance_interface_assignments 7.12.4.12. get_instance_interface_parameter_property 7.12.4.13. get_instance_interface_parameter_value 7.12.4.14. get_instance_interface_parameters 7.12.4.15. get_instance_interface_port_property 7.12.4.16. get_instance_interface_ports 7.12.4.17. get_instance_interface_properties 7.12.4.18. get_instance_interface_property 7.12.4.19. get_instance_interfaces 7.12.4.20. get_instance_parameter_property 7.12.4.21. get_instance_parameter_value 7.12.4.22. get_instance_parameter_values 7.12.4.23. get_instance_parameters 7.12.4.24. get_instance_port_property 7.12.4.25. get_instance_properties 7.12.4.26. get_instance_property 7.12.4.27. get_instances 7.12.4.28. is_instance_parameter_update_callback_enabled 7.12.4.29. remove_instance 7.12.4.30. set_instance_parameter_value 7.12.4.31. set_instance_parameter_values 7.12.4.32. set_instance_property
7.12.5. Instantiations x
7.12.5.1. add_instantiation_hdl_file 7.12.5.2. add_instantiation_interface 7.12.5.3. add_instantiation_interface_port 7.12.5.4. copy_instance_interface_to_instantiation 7.12.5.5. get_instantiation_assignment_value 7.12.5.6. get_instantiation_assignments 7.12.5.7. get_instantiation_hdl_file_properties 7.12.5.8. get_instantiation_hdl_file_property 7.12.5.9. get_instantiation_hdl_files 7.12.5.10. get_instantiation_interface_assignment_value 7.12.5.11. get_instantiation_interface_assignments 7.12.5.12. get_instantiation_interface_parameter_value 7.12.5.13. get_instantiation_interface_parameters 7.12.5.14. get_instantiation_interface_port_properties 7.12.5.15. get_instantiation_interface_port_property 7.12.5.16. get_instantiation_interface_ports 7.12.5.17. get_instantiation_interface_property 7.12.5.18. get_instantiation_interface_properties 7.12.5.19. get_instantiation_interface_sysinfo_parameter_value 7.12.5.20. get_instantiation_interface_sysinfo_parameters 7.12.5.21. get_instantiation_interfaces 7.12.5.22. get_instantiation_properties 7.12.5.23. get_instantiation_property 7.12.5.24. get_loaded_instantiation 7.12.5.25. import_instantiation_interfaces 7.12.5.26. load_instantiation 7.12.5.27. remove_instantiation_hdl_file 7.12.5.28. remove_instantiation_interface 7.12.5.29. remove_instantiation_interface_port 7.12.5.30. save_instantiation 7.12.5.31. set_instantiation_assignment_value 7.12.5.32. set_instantiation_hdl_file_property 7.12.5.33. set_instantiation_interface_assignment_value 7.12.5.34. set_instantiation_interface_parameter_value 7.12.5.35. set_instantiation_interface_port_property 7.12.5.36. set_instantiation_interface_sysinfo_parameter_value 7.12.5.37. set_instantiation_property
7.12.6. Components x
7.12.6.1. apply_component_preset 7.12.6.2. get_component_assignment 7.12.6.3. get_component_assignments 7.12.6.4. get_component_documentation_links 7.12.6.5. get_component_interface_assignment 7.12.6.6. get_component_interface_assignments 7.12.6.7. get_component_interface_parameter_property 7.12.6.8. get_component_interface_parameter_value 7.12.6.9. get_component_interface_parameters 7.12.6.10. get_component_interface_port_property 7.12.6.11. get_component_interface_ports 7.12.6.12. get_component_interface_property 7.12.6.13. get_component_interfaces 7.12.6.14. get_component_parameter_property 7.12.6.15. get_component_parameter_value 7.12.6.16. get_component_parameters 7.12.6.17. get_component_project_properties 7.12.6.18. get_component_project_property 7.12.6.19. get_component_property 7.12.6.20. get_loaded_component 7.12.6.21. load_component 7.12.6.22. reload_component_footprint 7.12.6.23. save_component 7.12.6.24. set_component_parameter_value 7.12.6.25. set_component_project_property
7.12.7. Connections x
7.12.7.1. add_connection 7.12.7.2. auto_connect 7.12.7.3. get_connection_parameter_property 7.12.7.4. get_connection_parameter_value 7.12.7.5. get_connection_parameters 7.12.7.6. get_connection_properties 7.12.7.7. get_connection_property 7.12.7.8. get_connections 7.12.7.9. remove_connection 7.12.7.10. remove_dangling_connections 7.12.7.11. set_connection_parameter_value
7.12.8. Top-level Exports x
7.12.8.1. add_interface 7.12.8.2. get_exported_interface_sysinfo_parameter_value 7.12.8.3. get_exported_interface_sysinfo_parameters 7.12.8.4. get_interface_port_property 7.12.8.5. get_interface_ports 7.12.8.6. get_interface_properties 7.12.8.7. get_interface_property 7.12.8.8. get_interfaces 7.12.8.9. get_port_properties 7.12.8.10. remove_interface 7.12.8.11. set_exported_interface_sysinfo_parameter_value 7.12.8.12. set_interface_port_property 7.12.8.13. set_interface_property
7.12.9. Validation x
7.12.9.1. set_validation_property 7.12.9.2. sync_sysinfo_parameters 7.12.9.3. validate_component 7.12.9.4. validate_component_interface 7.12.9.5. validate_connection 7.12.9.6. validate_instance 7.12.9.7. validate_instance_interface 7.12.9.8. validate_system 7.12.9.9. validate_component_footprint 7.12.9.10. reload_component_footprint
7.12.10. Miscellaneous x
7.12.10.1. auto_assign_base_addresses 7.12.10.2. auto_assign_irqs 7.12.10.3. auto_assign_system_base_addresses 7.12.10.4. get_parameter_properties 7.12.10.5. lock_avalon_base_address 7.12.10.6. send_message 7.12.10.7. set_use_testbench_naming_pattern 7.12.10.8. unlock_avalon_base_address 7.12.10.9. get_testbench_dutname 7.12.10.10. get_use_testbench_naming_pattern
7.12.11. Wire-Level Connection Commands x
7.12.11.1. set_wirelevel_expression 7.12.11.2. get_wirelevel_expressions 7.12.11.3. remove_wirelevel_expressions
7.13. Platform Designer Scripting Property Reference x
7.13.1. Connection Properties 7.13.2. Design Environment Type Properties 7.13.3. Direction Properties 7.13.4. Element Properties 7.13.5. Instance Properties 7.13.6. Interface Properties 7.13.7. Message Levels Properties 7.13.8. Module Properties 7.13.9. Parameter Properties 7.13.10. Parameter Status Properties 7.13.11. Parameter Type Properties 7.13.12. Port Properties 7.13.13. Project Properties 7.13.14. System Info Type Properties 7.13.15. Units Properties 7.13.16. Validation Properties 7.13.17. Interface Direction 7.13.18. File Set Kind 7.13.19. Access Type 7.13.20. Instantiation HDL File Properties 7.13.21. Instantiation Interface Duplicate Type 7.13.22. Instantiation Interface Properties 7.13.23. Instantiation Properties 7.13.24. Port Properties 7.13.25. VHDL Type
8. Component Interface Tcl Reference x
8.1. Platform Designer _hw.tcl Command Reference 8.2. Platform Designer _hw.tcl Property Reference 8.3. Component Interface Tcl Reference Revision History
8.1. Platform Designer _hw.tcl Command Reference x
8.1.1. Interfaces and Ports 8.1.2. Parameters 8.1.3. Interconnect Parameters 8.1.4. Display Items 8.1.5. Module Definition 8.1.6. Composition 8.1.7. Fileset Generation 8.1.8. Miscellaneous 8.1.9. SystemVerilog Interface Commands 8.1.10. Wire-Level Expression Commands
8.1.1. Interfaces and Ports x
8.1.1.1. add_interface 8.1.1.2. add_interface_port 8.1.1.3. get_interfaces 8.1.1.4. get_interface_assignment 8.1.1.5. get_interface_assignments 8.1.1.6. get_interface_ports 8.1.1.7. get_interface_properties 8.1.1.8. get_interface_property 8.1.1.9. get_port_properties 8.1.1.10. get_port_property 8.1.1.11. set_interface_assignment 8.1.1.12. set_interface_property 8.1.1.13. set_port_property 8.1.1.14. set_interface_upgrade_map
8.1.2. Parameters x
8.1.2.1. add_parameter 8.1.2.2. get_parameters 8.1.2.3. get_parameter_properties 8.1.2.4. get_parameter_property 8.1.2.5. get_parameter_value 8.1.2.6. get_string 8.1.2.7. load_strings 8.1.2.8. set_parameter_property 8.1.2.9. set_parameter_value
8.1.3. Interconnect Parameters x
8.1.3.1. set_domain_assignment 8.1.3.2. get_domain_assignment 8.1.3.3. get_domain_assignments 8.1.3.4. set_postadaptation_assignment 8.1.3.5. get_postadaptation_assignment 8.1.3.6. get_postadaptation_assignments
8.1.4. Display Items x
8.1.4.1. add_display_item 8.1.4.2. get_display_items 8.1.4.3. get_display_item_properties 8.1.4.4. get_display_item_property 8.1.4.5. set_display_item_property
8.1.5. Module Definition x
8.1.5.1. add_documentation_link 8.1.5.2. get_module_assignment 8.1.5.3. get_module_assignments 8.1.5.4. get_module_ports 8.1.5.5. get_module_properties 8.1.5.6. get_module_property 8.1.5.7. send_message 8.1.5.8. set_module_assignment 8.1.5.9. set_module_property 8.1.5.10. add_hdl_instance 8.1.5.11. package
8.1.6. Composition x
8.1.6.1. add_instance 8.1.6.2. add_connection 8.1.6.3. get_connections 8.1.6.4. get_connection_parameters 8.1.6.5. get_connection_parameter_value 8.1.6.6. get_instances 8.1.6.7. get_instance_interfaces 8.1.6.8. get_instance_interface_ports 8.1.6.9. get_instance_interface_properties 8.1.6.10. get_instance_property 8.1.6.11. set_instance_property 8.1.6.12. get_instance_properties 8.1.6.13. get_instance_interface_property 8.1.6.14. get_instance_parameters 8.1.6.15. get_instance_parameter_property 8.1.6.16. get_instance_parameter_value 8.1.6.17. get_instance_port_property 8.1.6.18. set_connection_parameter_value 8.1.6.19. set_instance_parameter_value
8.1.7. Fileset Generation x
8.1.7.1. add_fileset 8.1.7.2. add_fileset_file 8.1.7.3. set_fileset_property 8.1.7.4. get_fileset_file_attribute 8.1.7.5. set_fileset_file_attribute 8.1.7.6. get_fileset_properties 8.1.7.7. get_fileset_property 8.1.7.8. get_fileset_sim_properties 8.1.7.9. set_fileset_sim_properties 8.1.7.10. create_temp_file
8.1.8. Miscellaneous x
8.1.8.1. check_device_family_equivalence 8.1.8.2. get_device_family_displayname 8.1.8.3. get_qip_strings 8.1.8.4. set_qip_strings
8.1.9. SystemVerilog Interface Commands x
8.1.9.1. add_sv_interface 8.1.9.2. get_sv_interfaces 8.1.9.3. get_sv_interface_property 8.1.9.4. get_sv_interface_properties 8.1.9.5. set_sv_interface_property
8.1.10. Wire-Level Expression Commands x
8.1.10.1. set_wirelevel_expression 8.1.10.2. get_wirelevel_expressions 8.1.10.3. remove_wirelevel_expressions
8.2. Platform Designer _hw.tcl Property Reference x
8.2.1. Script Language Properties 8.2.2. Interface Properties 8.2.3. SystemVerilog Interface Properties 8.2.4. Instance Properties 8.2.5. Parameter Properties 8.2.6. Parameter Type Properties 8.2.7. Parameter Status Properties 8.2.8. Port Properties 8.2.9. Direction Properties 8.2.10. Display Item Properties 8.2.11. Display Item Kind Properties 8.2.12. Display Hint Properties 8.2.13. Module Properties 8.2.14. Fileset Properties 8.2.15. Fileset Kind Properties 8.2.16. Callback Properties 8.2.17. File Attribute Properties 8.2.18. File Kind Properties 8.2.19. File Source Properties 8.2.20. Simulator Properties 8.2.21. Port VHDL Type Properties 8.2.22. System Info Type Properties 8.2.23. Design Environment Type Properties 8.2.24. Units Properties 8.2.25. Operating System Properties 8.2.26. Quartus.ini Type Properties
1. Creating a System with Platform Designer
2. Creating a Board Support Package with BSP Editor
3. Creating Platform Designer Components
4. Optimizing Platform Designer System Performance
5. Platform Designer Interconnect
6. Platform Designer System Design Components
7. Platform Designer Command-Line Utilities
8. Component Interface Tcl Reference
9. Intel® Quartus® Prime Pro Edition User Guide: Platform Designer Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

1.14.4. Files Generated for Platform Designer Systems

The Intel® Quartus® Prime Pro Edition software generates the following output file structure for Platform Designer systems. Platform Designer automatically adds the generated .qsys system file to the open Intel® Quartus® Prime project following generation.
Figure 49. Files generated for Platform Designer Systems
Table 19.  Files Generated for Platform Designer Systems

File Name

Description

<your_system>.qsys

The Platform Designer system.

<your_subsystem>.qsys

The Platform Designer subsystem.

ip/

Contains the parameter files for the IP components in the system and subsystems.
<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
<your_system>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<your_system>.qgsimc

Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL.

<your_system>.qgsynth

Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL.

<your_system>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Intel® Quartus® Prime software.

<your_system>.csv Contains information about the upgrade status of the IP component.

your_system.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Block Diagram Files (.bdf).

<your_system<>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<your_system>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<your_system>_bb.v Use the Verilog black box (_bb.v) file as an empty module declaration for use as a black box.
<your_system>.sip Contains information required for NativeLink simulation of IP components. Add the .sip file to your Intel® Quartus® Prime Standard Edition project to enable NativeLink for supported devices. The Intel® Quartus® Prime Pro Edition software does not support NativeLink simulation.
<your_system>_inst.v or _inst.vhd HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<your_system>.regmap If the IP contains register information, the Intel® Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of host and agent interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console.
<your_system>.svd

Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Platform Designer system.

During synthesis, the Intel® Quartus® Prime software stores the .svd files for agent interface visible to the System Console hosts in the .sof file in the debug session. System Console reads this section, which Platform Designer can query for register map information. For system agents, Platform Designer can access the registers by name.

<your_system>.v <your_ip>.vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation.
mentor/

Contains a ModelSim* script msim_setup.tcl to set up and run a simulation.

aldec/

Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation.

/synopsys/vcs

/synopsys/vcsmx

Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS* MX simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

/xcelium

Contains a shell script xcelium_setup.sh and other setup files to set up and run a Xcelium* simulation.

/common

Contains a set of Tcl files, <simulator>_files.tcl, which provide all design related simulation information required by a corresponding simulation script. The Tcl file contains designs from current system-level hierarchy, and references to sub-systems and IP components.

/submodules Contains HDL files for the IP core submodule.
<IP submodule>/ For each generated IP submodule directory, Platform Designer generates /synth and /sim sub-directories.

For generated IP components, Platform Designer appends unique suffixes (hashes) to the IP component’s RTL file name to ensure uniqueness of the RTL file and IP component file. The uniqueness of the files is necessary because a system can have multiple instances of the same IP, each with different parameterizations, resulting in multiple variances of the IP component. The hash derives from the parameterization that you specify for the IP component. This methodology ensures no collisions between the multiple variants of the same IP.

Level Two Title