Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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5.1.12. Platform Designer Address Decoding

Address decoding logic forwards appropriate addresses to each agent.

Address decoding logic simplifies component design in the following ways:

  • The interconnect selects an agent whenever it is being addressed by a host. Agent components do not need to decode the address to determine when they are selected.
  • Agent addresses are properly aligned to the agent interface.
  • Changing the system memory map does not involve manually editing HDL.
Figure 166. Address Decoding for One Host and Two AgentsIn this example, Platform Designer generates separate address decoding logic for each host in a system. The address decoding logic processes the difference between the host address width (<M>) and the individual agent address widths (<S>) and (<T>). The address decoding logic also maps only the necessary host address bits to access words in each agent’s address space.

Platform Designer controls the base addresses with the Base setting of active components on the System View tab. The base address of an agent component must be a multiple of the address span of the component. This restriction is part of the Platform Designer interconnect to allow the address decoding logic to be efficient, and to achieve the best possible fMAX.

Figure 167. Address Decoding Base Settings