Visible to Intel only — GUID: mwh1409959473818
Ixiasoft
Visible to Intel only — GUID: mwh1409959473818
Ixiasoft
6.11.3. Avalon® Streaming FIFO IP Buffer Fill Level
The Avalon® Streaming Dual-Clock FIFO IP has two fill levels, one in each clock domain. Due to the latency of the clock crossing logic, the fill levels reported in the input and output clock domains may be different for any instance. In both cases, the fill level may report badly for the clock domain; that is, the fill level is reported high in the input clock domain, and low in the output clock domain.
The Avalon® Streaming Dual-Clock FIFO IP has an output pipeline stage to improve fMAX. This output stage is accounted for when calculating the output fill level, but not when calculating the input fill level. Therefore, the best measure of the amount of data in the FIFO is by the fill level in the output clock domain. The fill level in the input clock domain represents the amount of space available in the FIFO (available space = FIFO depth – input fill level).