Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.11.3. Avalon® Streaming FIFO IP Buffer Fill Level

You can obtain the fill level of the Avalon® Streaming FIFO IP buffer via the optional Avalon® memory mapped control and status interface. Turn on the Use fill level parameter (Use sink fill level and Use source fill level in the Avalon® Streaming Dual-Clock FIFO IP) and read the fill_level register.

The Avalon® Streaming Dual-Clock FIFO IP has two fill levels, one in each clock domain. Due to the latency of the clock crossing logic, the fill levels reported in the input and output clock domains may be different for any instance. In both cases, the fill level may report badly for the clock domain; that is, the fill level is reported high in the input clock domain, and low in the output clock domain.

The Avalon® Streaming Dual-Clock FIFO IP has an output pipeline stage to improve fMAX. This output stage is accounted for when calculating the output fill level, but not when calculating the input fill level. Therefore, the best measure of the amount of data in the FIFO is by the fill level in the output clock domain. The fill level in the input clock domain represents the amount of space available in the FIFO (available space = FIFO depth – input fill level).