Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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5.10.7. Data Buses

Narrow bus transfers are supported. AXI write strobes can have any pattern that is compatible with the address and size information. Intel recommends that transactions to Avalon® slaves follow Avalon® byteenable limitations for maximum compatibility.
Note: Byte 0 is always bits [7:0] in the interconnect, following AXI's and Avalon® 's byte (address) invariance scheme.