Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/04/2021
Public

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5.1.5.2.2. Fixed Priority Arbitration with AXI Masters and Avalon® Memory Mapped Agents

When an AXI master is connected to a designated fixed priority arbitration Avalon® memory mapped agent, Platform Designer interconnect automatically instantiates an intermediary multiplexer in front of the Avalon® memory mapped agent.

Since AXI masters have separate read and write channels, each channel appears as two separate masters to the Avalon® memory mapped agent. To support fairness between the AXI master’s read and write channels, the instantiated round-robin intermediary multiplexer arbitrates between simultaneous read and write commands from the AXI master to the fixed-priority Avalon® memory mapped agent.

Figure 162. Intermediary Multiplexer Between AXI Master and Avalon® Memory Mapped Agent

When an AXI master is connected to a fixed priority AXI slave, the master’s read and write channels are directly connected to the AXI slave’s fixed-priority multiplexers. In this case, there is one multiplexer for the read command, and one multiplexer for the write command and therefore an intermediary multiplexer is not required.

The red rectangles indicate placement of the intermediary multiplexer between the AXI master and Avalon® Memory Mapped agent due to the separate read and write channels of the AXI master.