AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

B.1.1. Testbench Modules

The top-level of the testbench instantiates the following main modules:
  • altpcietb_bfm_rp_gen5x16.sv —This is the Root Port PCIe* BFM.
    //Directory path
    <project_dir>/intel_rtile_pcie_ast_0_example_design/pcie_ed_tb/ip/pcie_ed_tb/dut_pcie_tb_ip/intel_rtile_pcie_tbed_<ver>/sim
  • pcie_ed_dut.ip: This is the Endpoint design with the parameters that you specify.
    //Directory path
    <project_dir>/intel_rtile_pcie_ast_0_example_design/ip/pcie_ed
  • pcie_ed_pio0.ip: This module is a target and initiator of transactions for the PIO design example.
    //Directory path
    <project_dir>/intel_rtile_pcie_ast_0_example_design/ip/pcie_ed

In addition, the testbench has routines that perform the following tasks:

  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a PCI Express reset at start up.