AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 790711
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* 4. IP Architecture and Functional Description 5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters 6. Interfaces and Signals 7. Register Descriptions 8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Specifications B. Simulating the Design Example
1. Introduction x
1.1. Goal of the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.2. Intended Audience for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. What is PCI Express* ? 1.4. What are the Intel® FPGA IPs for PCI Express* ? 1.5. What is the AXI Streaming Intel® FPGA IP for PCI Express* ? 1.6. Example Use Models 1.7. Design Flow Requirements
1.7. Design Flow Requirements x
1.7.1. Design Software 1.7.2. Hardware
2. Features x
2.1. Supported Features 2.2. Device Family Support 2.3. Performance
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express* x
3.1. Download and Install Quartus Software 3.2. Obtain and Install Intel FPGA IPs and Licenses 3.3. Configure and Generate the AXI Streaming Intel® FPGA IP for PCI Express* 3.4. About the AXI Streaming Intel® FPGA IP for PCI Express Design Examples 3.5. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces 3.6. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.7. Compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.8. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.9. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.10. Verification with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant 3.11. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.4. About the AXI Streaming Intel® FPGA IP for PCI Express Design Examples x
3.4.1. Functional Description for the Programmed Input/Output (PIO) Design Example 3.4.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 3.4.3. Functional Description for the Performance Design Example
3.5. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces x
3.5.1. Clocking and Resets 3.5.2. Application Packet Datapath 3.5.3. Enabling Additional Features 3.5.4. Enabling Optional Interfaces
3.6. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.6.1. Simulating the Design Example
3.6.1. Simulating the Design Example x
3.6.1.1. Steps to Run Simulations
3.6.1.1. Steps to Run Simulations x
3.6.1.1.1. VCS* Simulator
3.8. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.8.1. Installing the Linux Kernel Driver
3.9. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.9.1. Running the Design Example
3.9.1. Running the Design Example x
3.9.1.1. Running the PIO Design Example
3.11. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant x
3.11.1. Debugging Link Training Issues 3.11.2. Debugging Data Transfer and Performance Issues
3.11.1. Debugging Link Training Issues x
3.11.1.1. Operating System Tools and Utilities 3.11.1.2. Signal Tap Logic Analyzer 3.11.1.3. Additional Debug Tools
3.11.2. Debugging Data Transfer and Performance Issues x
3.11.2.1. Advanced Error Reporting (AER) 3.11.2.2. Second-Level Debug Tools
4. IP Architecture and Functional Description x
4.1. Clocks and Resets 4.2. PCIe Hard IP (HIP) 4.3. HIP Interface (IF) Adaptor 4.4. Application Error Reporting 4.5. Debug Toolkit and Hard IP (HIP) Reconfiguration Interface 4.6. Configuration Space Extension 4.7. Control Shadow 4.8. Configuration Intercept Interface 4.9. Power Management 4.10. Legacy Interrupt 4.11. Credit Handling 4.12. Completion Timeout 4.13. Transaction Ordering 4.14. Page Request Service (PRS) Events 4.15. TX Non-Posted Metering Requirement on Application 4.16. MSI Pending 4.17. D-State Status 4.18. Configuration Retry Status Enable 4.19. AXI-Streaming Interface 4.20. Precision Time Measurement (PTM) [F/R-Tiles Only]
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters x
5.1. Parameter Editor Parameters
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. Application Packet Interface 6.4. Configuration Extension Bus Interface 6.5. Configuration Intercept Interface 6.6. Function Level Reset Interface 6.7. Control Shadow Interface (st_ctrlshadow) 6.8. Completion Timeout Interface (st_cplto) 6.9. Miscellaneous Signals 6.10. Control and Status Register Responder Interface (lite_csr) 6.11. Error Interface (st_err) 6.12. VF Error Flag Interface (vf_err/sent_vfnonfatalmsg) 6.13. VIRTIO PCI* Configuration Access Interface 6.14. Serial Data Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. Application Packet Interface x
6.3.1. Header Format 6.3.2. Prefix Format 6.3.3. Function Number Format 6.3.4. BAR Number Format 6.3.5. Data and Header Packing Schemes 6.3.6. Application Packet Transmit Interface (st_tx) 6.3.7. Application Packet Receive Interface (st_rx) 6.3.8. Flow Control Credit Handling
6.3.5. Data and Header Packing Schemes x
6.3.5.1. HIP Native Mode Packing 6.3.5.2. Compact Packing 6.3.5.3. Simple Packing
6.3.5.1. HIP Native Mode Packing x
6.3.5.1.1. Application Logic Guidelines for the AXI Streaming TX Interface in HIP Native Mode (R-Tile) 6.3.5.1.2. Application Logic Guidelines for the AXI Streaming RX Interface in HIP Native Mode
6.3.5.2. Compact Packing x
6.3.5.2.1. Application Logic Guidelines for the AXI Streaming TX Interface in Compact Mode (P/R-Tiles) 6.3.5.2.2. Application Logic Guidelines for the AXI Streaming RX Interface in Compact Mode (P/R-Tiles)
6.3.5.3. Simple Packing x
6.3.5.3.1. Application Logic Guidelines for the AXI Streaming TX Interface in Simple Mode (P/R-Tiles) 6.3.5.3.2. Application Logic Guidelines for the AXI Streaming RX Interface in Simple Mode (P/R-Tiles)
6.3.8. Flow Control Credit Handling x
6.3.8.1. Application Transmit Flow Control Credit Interface (st_txcrdt) 6.3.8.2. Application Receive Flow Control Credit Interface (st_rxcrdt) (R-Tile Only)
6.4. Configuration Extension Bus Interface x
6.4.1. Configuration Extension Bus Request Interface (st_cebreq) 6.4.2. Configuration Extension Bus Response Interface (st_cebresp)
6.5. Configuration Intercept Interface x
6.5.1. Configuration Intercept Request Interface (st_ciireq) 6.5.2. Configuration Intercept Response Interface (st_ciiresp)
6.6. Function Level Reset Interface x
6.6.1. Function Level Reset Received Interface (st_flrrcvd) 6.6.2. Function Level Reset Completion Interface (st_flrcmpl)
6.13. VIRTIO PCI* Configuration Access Interface x
6.13.1. VIRTIO PCI* Config Access Request Interface (st_virtio_pcicfgreq) 6.13.2. VIRTIO PCI* Config Access Completion Interface (st_virtio_pcicfgcmpl)
7. Register Descriptions x
7.1. Register Address Map 7.2. PCIe Configuration Space 7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map
7.2. PCIe Configuration Space x
7.2.1. PCIe Configuration Space Registers
7.3. AXI Streaming Intel® FPGA IP for PCI Express* Soft Register Address Map x
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers 7.3.2. IP Debug Registers 7.3.3. IP Performance Monitor Registers
7.3.1. AXI Streaming Intel® FPGA IP for PCI Express* Control Registers x
7.3.1.1. AXI Streaming Intel® FPGA IP for PCI Express* Version 7.3.1.2. AXI Streaming Intel® FPGA IP for PCI Express* Features 7.3.1.3. AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes 7.3.1.4. HOT PLUG GEN CTRL 7.3.1.5. POWER MANAGEMENT CTRL 7.3.1.6. LEGACY INTERRUPT CTRL 7.3.1.7. CFG REG IA CTRL 7.3.1.8. CFG REG IA FN NUM 7.3.1.9. CFG REG IA WRDATA 7.3.1.10. CFG REG IA RDDATA 7.3.1.11. PRS CTRL 7.3.1.12. MSI PENDING CTRL 7.3.1.13. MSI PENDING 7.3.1.14. D-STATE STS 7.3.1.15. CFG RETRY CTRL
7.3.2. IP Debug Registers x
7.3.2.1. HIP Status 7.3.2.2. HIP BP CYCLES 7.3.2.3. HIA BP CYCLES 7.3.2.4. APP BP CYCLES 7.3.2.5. HIA RX BP CYCLES
7.3.3. IP Performance Monitor Registers x
7.3.3.1. PERFMON CTRL 7.3.3.2. TX MRD TLP 7.3.3.3. TX MWR TLP 7.3.3.4. TX MSG TLP 7.3.3.5. TX CFGWR TLP 7.3.3.6. TX CFGRD TLP 7.3.3.7. RX MRD TLP 7.3.3.8. RX MWR TLP 7.3.3.9. RX MSG TLP 7.3.3.10. RX CFGWR TLP 7.3.3.11. RX CFGRD TLP 7.3.3.12. TX MEM DATA 7.3.3.13. TX CPL DATA 7.3.3.14. RX MEM DATA 7.3.3.15. RX CPL DATA
A. Specifications x
A.1. P-Tile Specifications A.2. F-Tile Specifications A.3. R-Tile Specifications
A.1. P-Tile Specifications x
A.1.1. P-Tile Completion Buffer Size A.1.2. Power Management A.1.3. MSI and MSI-X
A.2. F-Tile Specifications x
A.2.1. F-Tile Completion Buffer Size A.2.2. Power Management
A.3. R-Tile Specifications x
A.3.1. R-Tile Completion Buffer Size A.3.2. Power Management A.3.3. MSI and MSI-X
B. Simulating the Design Example x
B.1. Testbench
B.1. Testbench x
B.1.1. Testbench Modules B.1.2. Test Driver Module B.1.3. PIO Design Example Testbench B.1.4. Root Port BFM
1. Introduction
2. Features
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express*
4. IP Architecture and Functional Description
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters
6. Interfaces and Signals
7. Register Descriptions
8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Specifications
B. Simulating the Design Example

3.11.1.2. Signal Tap Logic Analyzer

Using the Signal Tap Logic Analyzer, you can monitor the following top-level signals from the AXI Streaming Intel® FPGA IP for PCI Express* to confirm the failure symptom for any port type (Root Port, Endpoint) and configuration (Gen5/Gen4/Gen3).

Table 23.  Top-Level Signals to be Monitored for Debugging
Signal Description Expected value for successful link up
p<n>_pin_perst_n where n = 0, 1 Active-low asynchronous output signal from the PCIe* IP. It is derived from the pin_perst_n input signal. 1'b1
ninit_done Active-low asynchronous output signal from the Reset Release Intel FPGA IP. High indicates that the FPGA device is not yet fully configured, and low indicates the device has been configured and is in normal operating mode. For more details on the Reset Release Intel FPGA IP. 1'b0
p<n>_reset_status_n where n = 0, 1 Active-low output signal from the IP, synchronous to coreclkout_hip_toapp of the IP. The reset_status_n output of HIP drives this signal. Held low until pin_perst_n is deasserted and the PCIe Hard IP comes out of reset. When port bifurcation is used, there is one such signal for each port. The application logic can use this signal to drive its reset network. 1’b1
p<n>_ss_app_linkup where n = 0,1 Indicates the Physical link layer is up. Synchronous to coreclkout_hip_toapp clock of the IP. 1'b1
p<n>_ss_app_dlup where n = 0, 1 Indicates the data link layer is up. Synchronous to coreclkout_hip_toapp clock of the IP. 1’b1
p<n>_ss_app_ltssmstate[5:0] where n = 0, 1 (F/R-Tile) Indicates the LTSSM state, synchronous to coreclkout_hip of the Hard IP. Refer to the description for ltssm_state_o[5:0] below for the encodings of these state signals. 6’b11 (L0)
p<n>_ss_app_serr where n = 0, 1

Indicates system error is detected. Synchronous to coreclkout_hip_toapp clock of the IP.

EP mode: Asserted when the P-Tile PCIe Hard IP sends a message of correctable/non-fatal/fatal error.

 1’b0
link_up_o Active-high output signal from the PCIe Hard IP, synchronous to coreclkout_hip clock of the HardIP. Indicates that the Physical Layer link is up. (This signal is currently available at the Hard IP interface). 1’b1
dl_up_o Active-high output signal from the PCIe Hard IP, synchronous to coreclkout_hip of the Hard IP. Indicates that the Data Link Layer is active. 1’b1

ltssm_state_o[5:0] (P-Tile)

Indicates the LTSSM state, synchronous to coreclkout_hip of the Hard IP. (This signal is currently available at the Hard IP interface)

  • 6'h00: S_DETECT_QUIET
  • 6'h01: S_DETECT_ACT
  • 6'h02: S_POLL_ACTIVE
  • 6'h03: S_POLL_COMPLIANCE
  • 6'h04: S_POLL_CONFIG
  • 6'h05: S_PRE_DETECT_QUIET
  • 6'h06: S_DETECT_WAIT
  • 6'h07: S_CFG_LINKWD_START
  • 6'h08: S_CFG_LINKWD_ACCEPT
  • 6'h09: S_CFG_LANENUM_WAIT
  • 6'h0A: S_CFG_LANENUM_ACCEPT
  • 6'h0B: S_CFG_COMPLETE
  • 6'h0C: S_CFG_IDLE
  • 6'h0D: S_RCVRY_LOCK
  • 6'h0E: S_RCVRY_SPEED
  • 6'h0F: S_RCVRY_RCVRCFG
  • 6'h10: S_RCVRY_IDLE
  • 6'h11: S_L0
  • 6'h12: S_L0S
  • 6'h13: S_L123_SEND_EIDLE
  • 6'h14: S_L1_IDLE
  • 6'h15: S_L2_IDLE
  • 6'h16: S_L2_WAKE
  • 6'h17: S_DISABLED_ENTRY
  • 6'h18: S_DISABLED_IDLE
  • 6'h19: S_DISABLED
  • 6'h1A: S_LPBK_ENTRY
  • 6'h1B: S_LPBK_ACTIVE
  • 6'h1C: S_LPBK_EXIT
  • 6'h1D: S_LPBK_EXIT_TIMEOUT
  • 6'h1E: S_HOT_RESET_ENTRY
  • 6'h1F: S_HOT_RESET
  • 6'h20: S_RCVRY_EQ0
  • 6'h21: S_RCVRY_EQ1
  • 6'h22: S_RCVRY_EQ2
  • 6'h23: S_RCVRY_EQ3
 6’b11 (L0)
p<n>_ss_app_surprise_down_err where n=0,1 Active high asynchronous output signal. Indicates that a surprise down event is occurring in the HardIP controller. This error event is triggered when the PHY layer reports to the Data Link Layer that the link is down. 1’b0
p<n>_ss_app_rx_par_err where n=0,1 Indicates a parity error detected at the input of the HIP’S RX buffer. Asserts for a single cycle. Synchronous to the axi_st_clk clock.
Note: Application must reset the HardIP if this occurs because parity errors can leave the Hard IP in an unknown state.
1’b0
p<n>_ss_app_tx_par_err where n=0,1 Indicates a parity error during TX TLP transmission at the HIP. Asserts for a single cycle. Synchronous to the axi_st_clk clock. 1’b0
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