AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.3.8. RX MWR TLP

The register indicates the number of memory write TLPs received by the IP.

Default Value: 0x000AXI0_0000

Table 98.  RX MWR TLP Registers
Register Name Bit Attribute User Side Description
RX MWR TLP 31-0 RW1C Number of Memory Write TLPs