AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.3.9. RX MSG TLP

The register indicates the number of message TLPs received by the IP.

Default Value: 0x0000_0000

Table 99.  RX MSG TLP Registers
Register Name Bit Attribute User Side Description
RX MSG TLP 31-0 RW1C Number of Message Write TLPs