AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.1.11. PRS CTRL

The IP generates Page Request Service (PRS) events to the QHIP based on the settings of this PRS CTRL register.

Usage of this control register is applicable only when operating as Endpoint and with TLP Bypass disabled.

Default Value: 0x0000_0000

Table 82.  Page Request Service (PRS) Control Register
Register Name Bit Attribute User Side Description
PRS CTRL 0 RW

Generate Page Request Service (PRS) Event

Writing '1' to this bit triggers PRS event.

Write to this bit is ignored if bit is already set.

The IP generates PRS event and clears this bit indicating requested operation complete.

5-1

RW

PF Number

Indicates Physical Function Number of the PRS event.

Note: Current Quartus release limits to max 8 PFs only.
7-6 RsvdZ Reserved
8 RW

Response Failure:

Indicate that the function has received a PRG response failure.

9 RW

Unexpected Page Request Group Index:

Indicate that the function has received a response with Unexpected Page Request Group Index.

10 RW

Stopped:

Indicate that the function has completed all previously issued page requests and that it has stopped requests for additional pages. Only valid when the PRS enable bit is clear.

19-11 RsvdZ Reserved
24-20 RW

Slot Number

Indicates Slot Number of function generating Interrupt.

31-25 RsvdZ Reserved