AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

A.1.1. P-Tile Completion Buffer Size

P-tile PCIe Hard IP implements Completion Buffers for Header and Data for each PCIe core/port. In Endpoint mode, when Completion credits are infinite, user application needs to manage the number of outstanding requests according to the buffer size to prevent overflow and lost Completions packets.

Table 106.  P-tile Completion Buffer Size
Completion Buffer Depth Width
Port 0 Cpl header 1144 NA
Port 0 Cpl data 1444 256
Port 1 Cpl header 572 NA
Port 1 Cpl data 1444 128
Port 2 Cpl header 286 NA
Port 2 Cpl data 1444 64
Port 3 Cpl header 286 NA
Port 3 Cpl data 1444 64

Refer to section 4.4.8.1 of the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide.