Visible to Intel only — GUID: kli1700067330082
Ixiasoft
Visible to Intel only — GUID: kli1700067330082
Ixiasoft
6.9. Miscellaneous Signals
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
ss_app_serr | Output | axi_st_clk | Indicates System Error is detected. In TLP Bypass Mode indicates PL/DL/TL layer error detected by HardIP. |
ss_app_linkup | Output | axi_st_clk | When asserted, this signal indicates the link is up. |
ss_app_dlup | Output | axi_st_clk | Indicates Data Link Layer is UP. |
ss_app_int_status | Output | axi_st_clk | This signal drives legacy interrupts to the Application Layer. The source of the interrupt will be logged in the Root Port Interrupt Status registers in the Port Configuration and Status registers.
Note: Applicable only in Root Port Mode.
|
ss_app_surprise_down_err | Output | Async | Indicates that a surprise down event is occurring in the HardIP controller. |
ss_app_ltssmstate | Output | axi_st_clk | Indicates the LTSSM state. |
ss_app_rx_par_err | Output | axi_st_clk | Indicates a parity error detected at the input of the HIP’S RX buffer. Asserts for a single cycle. Note: Application must reset the HardIP if this occurs because parity errors can leave the HardIP in an unknown state. |
ss_app_tx_par_err | Output | axi_st_clk | Indicates a parity error during TX TLP transmission at the HIP. Asserts for a single cycle. |