Visible to Intel only — GUID: rvx1700067241067
Ixiasoft
Visible to Intel only — GUID: rvx1700067241067
Ixiasoft
6.2.1. Interface Clock Signals
Signal Name | Direction | EP/RP/BP | Description |
---|---|---|---|
refclk[1:0] | I | EP | These are the input reference clocks for the IP core. These clocks must be free-running. For more details on how to connect these clocks, refer to the section Clock Sharing in Bifurcation Modes. EP 100 MHz ± 300 ppm |
p<n>_axi_st_clk | I | EP | Global clock signal for AXI -ST interface. All AXI-ST signals are sampled on the rising edge of this clk. This clock drives main data path.
The frequency of this clock depends on the mode in which the IP is configured:
|
axi_lite_clk | I | EP | The global clock signal for the AXI-Lite interface. All AXI-Lite signals are sampled on the rising edge of p<n>_axi_lite_clk. This clock drives control and status register interfaces in the design. Frequency: 100-250 MHz (250 MHz default) |
coreclkout_hip_toapp | O | EP | The coreclkout_hip output of Hard IP drives this clock. Application can use this clock to generate PCIe* SS clocks. Gen5: 500 MHz Gen4: 500 MHz Gen3: 250 MHz Gen2/Gen1: Gen1/Gen2 is supported only via link down-training and not natively. Hence, the coreclkout_hip clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz. |
xcvr_reconfig_clk | I | EP | Clock for the PHY reconfiguration interface. This is an Avalon-MM interface. This optional interface is enabled when you turn on the Enable PHY Reconfiguration option in the PCIe Interfaces Settings tab. This interface is shared among all the cores. 50 MHz - 125 MHz (range) 100 MHz (recommended) |