AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.1.10. CFG REG IA RDDATA

This register holds read data from read operation initiated by the master using indirect access mechanism.

Default Value: 0x0000_0000

Table 81.  Configuration Register Indirect Access Write Data
Register Name Bit Attribute User Side Description
CFG REG IA RDDATA 31-0 RO

Read Data

Data read from configuration register with read access.

Master reads this register after read operation completion indicated by Initiate Access bit in CFG IA CTRL register.

The PF/VF and Miscellaneous HIP registers can be accessed through Indirect Access to the CFG REG IA registers. Selective registers are user accessible for specific features. Below are a few examples to show accesses to the CFG REG IA register fields:
  • Access PF1 Type 0 Configuration Header: Vendor ID:
    • CFG REG IA CTRL - Register Address (DW address)= 0x0
    • CFG REG IA FN NUM - Function Type = 'h0, PF Number = 'h1
  • Access VF2 of PF1 Type 0 Configuration Header: Command Register:
    • CFG REG IA CTRL - Register Address (DW address) = 0x1, (Byte address = 0x4)
    • CFG REG IA FN NUM - Function Type = 'h1, PF Number = 'h1, VF Number = 'h2