AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.3.8.2. Application Receive Flow Control Credit Interface (st_rxcrdt) (R-Tile Only)

The RX flow control credit interface is not available for P/F-Tiles. The Receive side of the IP operates on an AXI Streaming ready-valid handshake for P- and F-Tiles.

For R-Tile:
  • In HIP Native mode, the IP provides the RX flow control credit interface for the application logic to advertise the available credits in the application to the IP.
  • In non-HIP Native (Simple/Compact) mode, the receive side of the IP operates on an AXI streaming ready-valid handshake. There is no RX flow control credit interface available for the application logic in this mode.

In the R-Tile HIP Native mode, the RX flow control interface provides information on the application's available RX buffer space to the IP for header and data for Posted (P), Non-Posted (NP) and Completion (CPL) transactions. It reports the space available in a number of credits as defined by the PCIe Specification.

The Application logic must ensure that enough credits are provided to the IP initially. This is to prevent a performance impact caused by the lack of credits available between the IP and the Application logic. Depending on the number of P, NP and CPL transactions happening at the PCIe link level, a lack of credit scenario may happen if the number of credits advertised by the Application logic is less than the credits advertised by the IP to the link partner.

Flow control credits are available for the following TLP categories:
  • Posted (P) transactions: TLPs that do not require a response.
  • Non-posted (NP) transactions: TLPs that require a completion.
  • Completions (CPL): TLPs that respond to non-posted transactions.
Table 52.  Credits Advertised by the IP to the Link Partner in Endpoint ModeThe credit unit in this table follows the PCIe Specification where one credit = 4 DWs = 16 Bytes.
Port Posted Headers Posted Data Non-Posted Headers Non-Posted Data Completion Headers Completion Data
Port 0 784 1456 784 392 0 (infinite) 0 (infinite)
Port 1 392 760 392 196 0 (infinite) 0 (infinite)
Note: In some systems, there are broadcast Message TLPs being sent by the link partner during the PCIe enumeration process. Failing to properly initialize and return the corresponding credits from the application logic to the IP may cause enumeration issues due to the priority order between Message TLPs and the Completions required for Configuration TLPs. Application logic must ensure proper credits are returned to the IP for any TLP that it receives.
Table 53.  Categorization of Transaction Types
TLP Type Category
Memory Write Posted
Memory Read Non-Posted
Memory Read Lock
I/O Read
I/O Write
Configuration Read
Configuration Write
Fetch and Add AtomicOp
Message Posted
Completion Completion
Completion with Data
Completion Lock
Completion Lock with Data
Table 54.  Application Receive Flow Control Credit Interface
Signal Name Direction Clock Domain Description
ss_app_st_rxcrdt_tvalid Input axi_st_clk tvalid indicates that the credit information on tdata is valid.
ss_app_st_rxcrdt_tdata[18:0] Input axi_st_clk Carries the credit limit information and type of credit.

[15:0] - Credit Limit Value

[18:16] - Credit Type
  • 3'b000 - Posted Header Credit
  • 3'b001 - Non-Posted Header Credit
  • 3'b010 - Completion Header Credit
  • 3'b011 - Reserved
  • 3'b100 - Posted Data Credit
  • 3'b101 - Non-Posted Data Credit
  • 3'b110 - Completion Data Credit
  • 3'b111 - Reserved

The credit limit is first initialized to 0 for all the credit types.