GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP

The JTAG to Avalon® Master Bridge Intel FPGA IP provides access to the reconfiguration register space of the GTS through System Console. The Quartus® Prime software inserts the debug interconnect fabric to connect the JTAG interface to the GTS PMA.
To Enable the JTAG to Avalon® Master Bridge Intel FPGA IP Interface, follow these steps:
  1. In the Avalon® Memory-Mapped Interface tab of the GTS PMA/FEC Direct PHY Intel FPGA IP parameter editor, enable the following options:
    • Enable Avalon® Memory Mapped interface
    Figure 66.  Avalon® Memory-Mapped Interface Parameter Settings to Enable JTAG to Avalon® Master Bridge
  2. Instantiate JTAG to Avalon® Master Bridge Intel® FPGA IP instance from the IP Catalog. You use the IP to interface with the Avalon® interface.
    Figure 67. IP Catalog
  3. Connect the clock and reset signals to the i_reconfig_clk and i_reconfig_reset ports of the reconfiguration interface.
  4. Connect the other reconfiguration interface signals:
    • i_reconfig_write
    • i_reconfig_read
    • i_reconfig_address
    • i_reconfig_writedata
    • o_reconfig_readdata
    • i_reconfig_byteenable
    • o_reconfig_readdatavalid
    • o_reconfig_waitrequest
    to the equivalent JTAG to Avalon® Master Bridge Intel® FPGA IP reconfiguration signals.