GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.6.1. Clock Ports

The GTS PMA/FEC Direct PHY Intel FPGA IP supports two clock output ports.

The two clock output ports can each choose one of the three clock options described in Clock Outputs.

tx/rx_clkout

tx/rx_clkout is an output port that is enabled by default. You can select one of the three clock options described in Clock Outputs as the source for this port, by selecting TX/RX Clock Options > Selected tx/rx_clkout clock source on the TX Datapath Options tab.

tx/rx_clkout2

tx/rx_clkout2 is an additional output port that you can enable by turning on the Enable tx/rx_clkout2 port option in the parameter editor. You can select one of the three clock options as the source for this port, by selecting TX/RX Clock Options > Selected tx/rx_clkout clock source on the TX/RX Datapath Options tab.

Both the tx/rx_clkout and tx/rx_clkout2 outputs can be further divided by a factor of 1,2, or 4.

Figure 50. tx_clkout and tx_clkout2
Figure 51. rx_clkout and rx_clkout2

i_tx/rx_coreclkin

i_tx/rx_coreclkin is an input port for clocking the TX/RX core interface FIFO. Refer to Recommended Connection and Source for the recommended connections. The recommended source clock for o_tx/rx_clkout and o_tx/rx_clkout2 when connecting to i_tx/rx_coreclkin is shown in Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source. The recommended port connections details are shown in Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2.