Visible to Intel only — GUID: lqk1682636858434
Ixiasoft
Visible to Intel only — GUID: lqk1682636858434
Ixiasoft
3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source
Recommended Connection and Source table below shows recommended i_tx/rx_coreclkin connection and o_tx/rx_clkout and o_tx/rx_clkout2 source, based on the datapath clocking mode and double-width transfer selection.
Datapath Clocking Mode | Core Interface FIFO Mode | Enable TX/RX Double Width Transfer | Recommended tx/rx_coreclkin connection | Recommended tx/rx_clkout or tx/rx_clkout2 source | Division factor |
---|---|---|---|---|---|
PMA | Phase Compensation | No | o_tx/rx_clkout | Word clock | N/A |
Yes | o_tx/rx_clkout2 | Word clock | 2 | ||
Elastic | Yes | o_tx/rx_clkout2 or any other clock source from user | Word clock/User clock | 2 | |
No | o_tx/rx_clkout or any other clock source from user | Word clock/User clock | N/A | ||
System PLL | Phase Compensation | No | o_tx/rx_clkout | Sys PLL clock | N/A |
Yes | o_tx/rx_clkout | Sys PLL clock | 2 |
- When using system PLL clocking mode, both o_tx_clkout and o_rx_clkout can clock i_tx_coreclkin and i_rx_coreclkin.
-
When using PMA clocking mode, o_tx_clkout/2 must clock i_tx_coreclkin. o_rx_clkout/2 must clock i_rx_coreclkin. The only exception to this requirement in PMA clocking mode is for chip to chip applications where TX and RX share same reference clock source (that is, 0 PPM difference), o_tx_clkout or o_rx_clkout can clock both i_tx_coreclkin and i_rx_coreclkin.