GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath

The tx_parallel_data bit and rx_parallel_data bit width depends on the PMA width and Number of PMA lanes IP parameters. Use the following equation to determine the total tx_parallel_data or rx_parallel_data bit width:

Total tx_parallel_data or rx_parallel_data Bit Width Equation:

tx/rx_parallel_data[(80*N)-1:0]

Where:

  • N = Number of PMA lanes value from 1 to 4.

The tx/rx_parallel_data signals include the valid parallel data bits and other functionality bits, such as the data valid bit, the write enable for TX core interface FIFO in elastic mode bit, the RX deskew bit, and the alignment marker bits (for FEC mode). These signals travel to and from the FPGA fabric to the transceiver block, and are clocked by the same parallel clock. This parallel clock can be a PMA clock or System PLL clock.

Example 1: Total tx/rx_parallel_data Bit Width with 2 PMA Lanes (N=2) and 8-bit PMA Width (X=1)

tx_parallel_data [(80*2)-1:0] = tx_parallel_data [159:0]
rx_parallel_data [(80*2)-1:0] = rx_parallel_data [159:0]

Parallel Data Mapping information for TX and RX

Table 44.  Variable Definitions
Variable Values Description
N 1, 2, 4, 6, 8 Number of lanes
n 0 to N-1 N is the PMA index number
D D = PMA Width D is the data width value to calculate the total parallel data bits
Table 45.  PMA Direct Mode Parallel Data Calculations
PMA Configuration MSB LSB TX Parallel Data RX Parallel Data

PMA Width = 8, 10, 16, 20, 32

Single Width

79 Write Enable for TX Core FIFO in Elastic Mode 37 Data valid for RX Core FIFO in Elastic Mode37
38 + (80*n) TX PMA Interface Data Valid RX PMA Interface Data Valid
[D-1] + (80*n) 0 + (80*n) TX Data RX Data

PMA Width = 8, 10, 16, 20, 32

Double Width

79 Write Enable for TX Core FIFO in Elastic Mode37 Data valid for RX Core FIFO in Elastic Mode37
(40+D-1) + (80*n) 40 + (80*n) TX Data (Upper Data Bits) RX Data (Upper Data Bits)
38 + (80*n) TX PMA Interface Data Valid RX PMA Interface Data Valid
(D -1) + (80*n) 0 + (80*n) TX Data (Lower Data Bits) RX Data (Lower Data Bits)
Table 46.  FEC Direct Mode Parallel Data Calculations
MSB LSB TX Parallel Data RX Parallel Data
77 Alignment Marker -
72 40 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
38 TX PMA Interface Data Valid Bit RX PMA Interface Data Valid Bit
37 Alignment Marker Alignment Marker
32 2 TX Data (Lower Data Bits) RX Data (Lower Data Bits)
1 0 Sync Head
Table 47.  Example of Bit Mapping of TX Parallel Data Bits for PMA Direct Mode with PMA Width = 32
N (Number of Lanes) 1 2 4 TX Parallel Data
Bits 79 159 319

Write Enable for TX Core FIFO in Elastic Mode.

38 118 278 TX PMA Interface Data Valid
31:0 118:80 271:240 TX Data (Lower Data Bits)
71:40 151:120 311:280 TX Data (Upper Data Bits)
Table 48.  PCS Direct Mode — IEEE Parallel Data Calculations
MSB LSB TX Parallel Data RX Parallel Data
76 o_tx_mii_ready
74 i_tx_mii_c[7] o_rx_mii_c[7]
73 66 i_tx_mii_d[63:56] o_rx_mii_d[63:56]
65 i_tx_mii_c[6] o_rx_mii_c[6]
64 57 i_tx_mii_d[55:48] o_rx_mii_d[55:48]
56 i_tx_mii_c[5] o_rx_mii_c[5]
55 48 i_tx_mii_d[47:40] o_rx_mii_d[47:40]
47 i_tx_mii_c[4] o_rx_mii_c[4]
46 39 i_tx_mii_d[39:32] o_rx_mii_d[39:32]
38 i_tx_mii_valid o_rx_mii_valid
37 i_tx_mii_am o_rx_mii_am
35 i_tx_mii_c[3] o_rx_mii_c[3]
34 27 i_tx_mii_d[31:24] o_rx_mii_d[31:24]
26 i_tx_mii_c[2] o_rx_mii_c[2]
25 18 i_tx_mii_d[23:16] o_rx_mii_d[23:16]
17 i_tx_mii_c[1] o_rx_mii_c[1]
16 9 i_tx_mii_d[15:8] o_rx_mii_d[15:8]
8 i_tx_mii_c[0] o_rx_mii_c[0]
7 0 i_tx_mii_d[7:0] o_rx_mii_d[7:0]
Table 49.  PCS Direct Mode — IEEE_FLEXE_66/PCS66 Parallel Data Calculations
MSB LSB TX Parallel Data RX Parallel Data
76 o_tx_ready
71 39 i_txd[65:33] o_rxd[65:33]
38 i_tx_valid o_rx_valid
37 i_tx_am o_rx_am
32 0 i_txd[32:0] o_rxd[32:0]
37 Only available for PMA clocking and if TX/RX core FIFO is in elastic mode.