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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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3.3.4.1. RX PMA Interface Parameters
Figure 44. RX PMA Interface Options in Parameter Editor
Parameter | Values | Description |
---|---|---|
RX PMA Interface Parameters | ||
RX PMA interface FIFO mode | Register Elastic |
Selects the RX PMA Interface FIFO mode. Default value is Elastic. Refer to PMA Direct Mode Support for more information, |
Enable rx_pmaif_fifo_empty port | On/Off | Enables the port that indicates the RX PMA Interface FIFO's empty condition. Default value is Off. |
Enable rx_pmaif_fifo_pempty port | On/Off | Enables the port that indicates the RX PMA Interface FIFO's partially empty condition. Default value is Off. |
Enable rx_pmaif_fifo_pfull port | On/Off | Enables the port that indicates the RX PMA Interface FIFO's partially full condition. Default value is Off. |
RX Core Interface Parameters | ||
RX core interface FIFO mode | Phase compensation Elastic 0 |
Specifies the mode for the RX Core Interface FIFO. Default value is Phase compensation. |
Enable RX double width transfer | On/Off | Enables double width RX data transfer mode. In this mode, core logic can be clocked with a half rate clock. Default value is On. |
Enable rx_fifo_full port | On/Off | Enables the optional o_rx_fifo_full status output port. This signal indicates when the RX core FIFO has reached the full threshold. This signal is synchronous with o_rx_clkout. Default value is Off. |
Enable rx_fifo_empty port | On/Off | Enables the optional o_rx_fifo_empty status output port. This signal indicates when the RX core FIFO has reached the empty threshold. This signal is synchronous with o_rx_clkout. Default value is Off. |
Enable rx_fifo_pfull port | On/Off | Enables the optional o_rx_fifo_pfull status output port. This signal indicates when the RX core FIFO has reached the specified partially full threshold. Default value is Off. |
Enable rx_fifo_pempty port | On/Off | Enables the optional o_rx_fifo_pempty status output port. This signal indicates when the RX core FIFO has reached the specified partially empty threshold. Default value is Off. |
Enable rx_fifo_rd_en port | On/Off | Enables the optional i_rx_fifo_rd_en control input port. This port is used for Elastic FIFO mode. Asserting this signal enables the read from RX core FIFO. You must enable this read enable when using Elastic FIFO. Default value is Off. |
RX Clock Options | ||
Selected rx_clkout clock source | Word Clock RX User Clock Sys PLL Clock |
Specifies the o_rx_clkout output port source. Default value is Sys PLL Clock. |
Frequency of rx_clkout | Output | Displays the frequency of o_rx_clkout in MHz based on o_rx_clkout source selection. |
Enable rx_clkout2 port | On/Off | Enables the optional o_rx_clkout2 output clock. Default value is Off. |
Selected rx_clkout2 clock source | Word Clock RX User Clock Sys PLL Clock |
Specifies the o_rx_clkout output port source. Default value is Word Clock. |
rx_clkout2 clock div by | 1, 2, 4 | Selects the RX clock out 2 divider setting that divides out the o_rx_clkout2 output port source. Default value is 1. |
Frequency of rx_clkout2 | Output | Displays the frequency of o_rx_clkout2 in MHz based on o_rx_clkout2 source selection and o_rx_clkout2 clock divide by factor. |
RX User Clock Settings | ||
RX user clock div by | 12-139.5 | Division factor from Fvco of RX CDR to RX user clock. Values from 12 to 139.5 are acceptable in 0.5 increments. Default value is 100. |
RX user clock Frequency | Output | Displays the frequency of RX user clock in MHz based on RX user clock divide by factor. |